Script 'mail_helper' called by obssrc Hello community, here is the log from the commit of package CoreFreq for openSUSE:Factory checked in at 2023-01-06 17:06:11 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/CoreFreq (Old) and /work/SRC/openSUSE:Factory/.CoreFreq.new.1563 (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "CoreFreq" Fri Jan 6 17:06:11 2023 rev:20 rq:1056367 version:1.94.3 Changes: -------- --- /work/SRC/openSUSE:Factory/CoreFreq/CoreFreq.changes 2023-01-03 15:06:24.874877289 +0100 +++ /work/SRC/openSUSE:Factory/.CoreFreq.new.1563/CoreFreq.changes 2023-01-06 17:06:55.240641309 +0100 @@ -1,0 +2,10 @@ +Fri Jan 6 10:44:12 UTC 2023 - Dirk Müller <dmuel...@suse.com> + +- update to 1.94.3: + * [AMD][RMB] If UMC is quad channels then unpopulate odd channels + * [AMD][RPL] Provide Service Processor Vcore as workaround + * [UI] Auto size and lay performance capabilities window + * [UI] Adding comments to the EEO and R2H technologies + * [AMD][Raphael] 7950X3D, 7900X3D. support + +------------------------------------------------------------------- Old: ---- CoreFreq-1.94.1.tar.gz New: ---- CoreFreq-1.94.3.tar.gz ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ CoreFreq.spec ++++++ --- /var/tmp/diff_new_pack.iBvDpl/_old 2023-01-06 17:06:55.628643488 +0100 +++ /var/tmp/diff_new_pack.iBvDpl/_new 2023-01-06 17:06:55.632643510 +0100 @@ -17,7 +17,7 @@ Name: CoreFreq -Version: 1.94.1 +Version: 1.94.3 Release: 0 Summary: CPU monitoring software for 64-bit processors License: GPL-2.0-or-later ++++++ CoreFreq-1.94.1.tar.gz -> CoreFreq-1.94.3.tar.gz ++++++ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-1.94.1/README.md new/CoreFreq-1.94.3/README.md --- old/CoreFreq-1.94.1/README.md 2023-01-03 08:10:54.000000000 +0100 +++ new/CoreFreq-1.94.3/README.md 2023-01-06 11:52:32.000000000 +0100 @@ -70,7 +70,7 @@ * GNU Make tool * Linux Kernel Header files to build modules * Mandatory : `CONFIG_MODULES, CONFIG_SMP, CONFIG_X86_MSR` - * Optionally: `CONFIG_HOTPLUG_CPU, CONFIG_CPU_IDLE, CONFIG_CPU_FREQ, CONFIG_PM_SLEEP, CONFIG_DMI, CONFIG_XEN, CONFIG_AMD_NB, CONFIG_SCHED_MUQSS, CONFIG_SCHED_BMQ, CONFIG_SCHED_PDS, CONFIG_SCHED_ALT, CONFIG_SCHED_BORE` + * Optionally: `CONFIG_HOTPLUG_CPU, CONFIG_CPU_IDLE, CONFIG_CPU_FREQ, CONFIG_PM_SLEEP, CONFIG_DMI, CONFIG_XEN, CONFIG_AMD_NB, CONFIG_SCHED_MUQSS, CONFIG_SCHED_BMQ, CONFIG_SCHED_PDS, CONFIG_SCHED_ALT, CONFIG_SCHED_BORE, CONFIG_CACHY, CONFIG_ACPI, CONFIG_ACPI_CPPC_LIB` 2. Clone the source code into a working directory. `git clone https://github.com/cyring/CoreFreq.git` diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-1.94.1/corefreq-cli-rsc-en.h new/CoreFreq-1.94.3/corefreq-cli-rsc-en.h --- old/CoreFreq-1.94.1/corefreq-cli-rsc-en.h 2023-01-03 08:10:54.000000000 +0100 +++ new/CoreFreq-1.94.3/corefreq-cli-rsc-en.h 2023-01-06 11:52:32.000000000 +0100 @@ -1168,7 +1168,20 @@ #define RSC_TECHNOLOGIES_HYPERV_CODE_EN "Hypervisor" #define RSC_TECHNOLOGIES_WDT_CODE_EN "Watchdog Timer" +#define RSC_TECH_AMD_CPB_COMM_CODE_EN " Hardware Configuration::CpbDis " +#define RSC_TECH_INTEL_EEO_COMM_CODE_EN " Skylake::Power Control::EEO_Disable " +#define RSC_TECH_INTEL_R2H_COMM_CODE_EN " Skylake::Power Control::R2H_Disable " +#define RSC_TECH_INTEL_SMM_COMM_CODE_EN " Basic VMX Capabilities::SMM_DualMon " +#define RSC_TECH_AMD_SMM_COMM_CODE_EN " Hardware Configuration::SmmLock " +#define RSC_TECH_INTEL_WDT_COMM_CODE_EN " Intel ICH Family Watchdog Timer " +#define RSC_TECH_AMD_WDT_COMM_CODE_EN " AMD APM Watchdog Timer " +#define RSC_TECH_AMD_SVM_COMM_CODE_EN " AMD Secure Virtual Machine " +#define RSC_TECH_INTEL_VMX_COMM_CODE_EN " Intel Virtual Machine Extensions " +#define RSC_TECH_INTEL_VTD_COMM_CODE_EN " I/O MMU virtualization (Intel VT-d) " +#define RSC_TECH_AMD_V_COMM_CODE_EN " I/O MMU virtualization (AMD-Vi) " + #define RSC_PERF_MON_TITLE_CODE_EN " Performance Monitoring " +#define RSC_PERF_CAPS_TITLE_CODE_EN " Performance Capabilities " #define RSC_VERSION_CODE_EN "Version" #define RSC_COUNTERS_CODE_EN "Counters" #define RSC_GENERAL_CTRS_CODE_EN "General" @@ -1591,6 +1604,7 @@ #define RSC_MENU_ITEM_ISA_EXT_CODE_EN " ISA Extensions [I] " #define RSC_MENU_ITEM_TECH_CODE_EN " Technologies [t] " #define RSC_MENU_ITEM_PERF_MON_CODE_EN " Perf. Monitoring [o] " +#define RSC_MENU_ITEM_PERF_CAPS_CODE_EN " Perf. Capabilities [z] " #define RSC_MENU_ITEM_POW_THERM_CODE_EN " Power & Thermal [w] " #define RSC_MENU_ITEM_CPUID_CODE_EN " CPUID Hexa Dump [u] " #define RSC_MENU_ITEM_SYS_REGS_CODE_EN " System Registers [R] " @@ -1902,6 +1916,7 @@ "\t-i <#>\tMonitor Instructions\n" \ "\t-s\tPrint System Information\n" \ "\t-j\tPrint System Information (json-encoded)\n" \ + "\t-z\tPrint Performance Capabilities\n" \ "\t-M\tPrint Memory Controller\n" \ "\t-R\tPrint System Registers\n" \ "\t-m\tPrint Topology\n" \ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-1.94.1/corefreq-cli-rsc-fr.h new/CoreFreq-1.94.3/corefreq-cli-rsc-fr.h --- old/CoreFreq-1.94.1/corefreq-cli-rsc-fr.h 2023-01-03 08:10:54.000000000 +0100 +++ new/CoreFreq-1.94.3/corefreq-cli-rsc-fr.h 2023-01-06 11:52:32.000000000 +0100 @@ -368,7 +368,7 @@ #define RSC_LOCK_CODE_FR "BLOQU""\x89" #define RSC_ENABLE_CODE_FR " Actif" #define RSC_DISABLE_CODE_FR "Inactif" -#define RSC_CAPABILITIES_CODE_FR "Capacites" +#define RSC_CAPABILITIES_CODE_FR "Capacit""\xa9""s" #define RSC_LOWEST_CODE_FR "Faible" #define RSC_EFFICIENT_CODE_FR "Efficace" #define RSC_GUARANTEED_CODE_FR "Guarantie" @@ -548,7 +548,7 @@ #define RSC_FEATURES_CORE_MP_CODE_FR "Core Multi-Processing" #define RSC_FEATURES_CNXT_ID_CODE_FR "L1 Data Cache Context ID" #define RSC_FEATURES_CPPC_CODE_FR \ - "Collaborative Processor Performance Control" + "Contr""\xb4""le collaboratif des performances CPU" #define RSC_FEATURES_DCA_CODE_FR "Direct Cache Access" #define RSC_FEATURES_DE_CODE_FR "Debugging Extension" @@ -642,7 +642,20 @@ #define RSC_TECHNOLOGIES_HYPERV_CODE_FR "Hyperviseur" #define RSC_TECHNOLOGIES_WDT_CODE_FR "Compteur Watchdog" +#define RSC_TECH_AMD_CPB_COMM_CODE_FR RSC_TECH_AMD_CPB_COMM_CODE_EN +#define RSC_TECH_INTEL_EEO_COMM_CODE_FR RSC_TECH_INTEL_EEO_COMM_CODE_EN +#define RSC_TECH_INTEL_R2H_COMM_CODE_FR RSC_TECH_INTEL_R2H_COMM_CODE_EN +#define RSC_TECH_INTEL_SMM_COMM_CODE_FR RSC_TECH_INTEL_SMM_COMM_CODE_EN +#define RSC_TECH_AMD_SMM_COMM_CODE_FR RSC_TECH_AMD_SMM_COMM_CODE_EN +#define RSC_TECH_INTEL_WDT_COMM_CODE_FR RSC_TECH_INTEL_WDT_COMM_CODE_EN +#define RSC_TECH_AMD_WDT_COMM_CODE_FR RSC_TECH_AMD_WDT_COMM_CODE_EN +#define RSC_TECH_INTEL_VMX_COMM_CODE_FR RSC_TECH_INTEL_VMX_COMM_CODE_EN +#define RSC_TECH_AMD_SVM_COMM_CODE_FR RSC_TECH_AMD_SVM_COMM_CODE_EN +#define RSC_TECH_INTEL_VTD_COMM_CODE_FR RSC_TECH_INTEL_VTD_COMM_CODE_EN +#define RSC_TECH_AMD_V_COMM_CODE_FR RSC_TECH_AMD_V_COMM_CODE_EN + #define RSC_PERF_MON_TITLE_CODE_FR " Gestion de la performance " +#define RSC_PERF_CAPS_TITLE_CODE_FR " Capacit""\xa9""s de performances " #define RSC_VERSION_CODE_FR "Version" #define RSC_COUNTERS_CODE_FR "Compteurs" #define RSC_GENERAL_CTRS_CODE_FR "G""\xa9""n""\xa9""raux" @@ -661,7 +674,9 @@ #define RSC_PERF_MON_FID_CODE_FR "Legacy Frequency ID control" #define RSC_PERF_MON_VID_CODE_FR "Legacy Voltage ID control" #define RSC_PERF_MON_HWCF_CODE_FR "P-State Hardware Coordination Feedback" -#define RSC_PERF_MON_CPPC_CODE_FR "Collaborative Processor Performance Control" +#define RSC_PERF_MON_CPPC_CODE_FR \ + "Contr""\xb4""le collaboratif des performances du processeur" + #define RSC_PERF_MON_PCT_CODE_FR RSC_PERF_MON_PCT_CODE_EN #define RSC_PERF_MON_PSS_CODE_FR RSC_PERF_MON_PSS_CODE_EN #define RSC_PERF_MON_PPC_CODE_FR RSC_PERF_MON_PPC_CODE_EN @@ -962,6 +977,7 @@ #define RSC_MENU_ITEM_ISA_EXT_CODE_FR " Jeu Instructions [I] " #define RSC_MENU_ITEM_TECH_CODE_FR " Technologies [t] " #define RSC_MENU_ITEM_PERF_MON_CODE_FR " Gestion de Perf. [o] " +#define RSC_MENU_ITEM_PERF_CAPS_CODE_FR " Capacit""\xa9""s de Perf. [z] " #define RSC_MENU_ITEM_POW_THERM_CODE_FR " Puissance-Therm. [w] " #define RSC_MENU_ITEM_CPUID_CODE_FR " Extraction CPUID [u] " #define RSC_MENU_ITEM_SYS_REGS_CODE_FR " Registres Syst""\xa8""me [R] " @@ -1365,6 +1381,7 @@ "\t-i <#>\tMoniteur des Instructions\n" \ "\t-s\tImprimer les Informations du système\n" \ "\t-j\tImprimer les Informations (format json)\n" \ + "\t-z\tImprimer les Capacités de performances\n" \ "\t-M\tImprimer le Controlleur mémoire\n" \ "\t-R\tImprimer les Registres du système\n" \ "\t-m\tImprimer la Topologie\n" \ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-1.94.1/corefreq-cli-rsc.c new/CoreFreq-1.94.3/corefreq-cli-rsc.c --- old/CoreFreq-1.94.1/corefreq-cli-rsc.c 2023-01-03 08:10:54.000000000 +0100 +++ new/CoreFreq-1.94.3/corefreq-cli-rsc.c 2023-01-06 11:52:32.000000000 +0100 @@ -988,20 +988,31 @@ LDT(RSC_TECH_L2_HW_PREFETCH), LDT(RSC_TECH_L2_HW_CL_PREFETCH), LDT(RSC_TECHNOLOGIES_SMM), + LDT(RSC_TECH_INTEL_SMM_COMM), + LDT(RSC_TECH_AMD_SMM_COMM), LDT(RSC_TECHNOLOGIES_HTT), LDT(RSC_TECHNOLOGIES_EIST), LDT(RSC_TECHNOLOGIES_IDA), LDT(RSC_TECHNOLOGIES_TURBO), LDT(RSC_TECHNOLOGIES_TBMT3), LDT(RSC_TECHNOLOGIES_VM), + LDT(RSC_TECH_INTEL_VMX_COMM), + LDT(RSC_TECH_AMD_SVM_COMM), LDT(RSC_TECHNOLOGIES_IOMMU), + LDT(RSC_TECH_INTEL_VTD_COMM), + LDT(RSC_TECH_AMD_V_COMM), LDT(RSC_TECHNOLOGIES_SMT), LDT(RSC_TECHNOLOGIES_CNQ), LDT(RSC_TECHNOLOGIES_CPB), + LDT(RSC_TECH_AMD_CPB_COMM), LDT(RSC_TECHNOLOGIES_EEO), + LDT(RSC_TECH_INTEL_EEO_COMM), LDT(RSC_TECHNOLOGIES_R2H), + LDT(RSC_TECH_INTEL_R2H_COMM), LDT(RSC_TECHNOLOGIES_HYPERV), LDT(RSC_TECHNOLOGIES_WDT), + LDT(RSC_TECH_INTEL_WDT_COMM), + LDT(RSC_TECH_AMD_WDT_COMM), LDQ(RSC_TECH_HYPERV_NONE), LDQ(RSC_TECH_BARE_METAL), LDQ(RSC_TECH_HYPERV_XEN), @@ -1011,6 +1022,7 @@ LDQ(RSC_TECH_HYPERV_VMWARE), LDQ(RSC_TECH_HYPERV_HYPERV), LDT(RSC_PERF_MON_TITLE), + LDT(RSC_PERF_CAPS_TITLE), LDT(RSC_VERSION), LDT(RSC_COUNTERS), LDT(RSC_GENERAL_CTRS), @@ -1522,6 +1534,7 @@ LDT(RSC_MENU_ITEM_ISA_EXT), LDT(RSC_MENU_ITEM_TECH), LDT(RSC_MENU_ITEM_PERF_MON), + LDT(RSC_MENU_ITEM_PERF_CAPS), LDT(RSC_MENU_ITEM_POW_THERM), LDT(RSC_MENU_ITEM_CPUID), LDT(RSC_MENU_ITEM_SYS_REGS), diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-1.94.1/corefreq-cli-rsc.h new/CoreFreq-1.94.3/corefreq-cli-rsc.h --- old/CoreFreq-1.94.1/corefreq-cli-rsc.h 2023-01-03 08:10:54.000000000 +0100 +++ new/CoreFreq-1.94.3/corefreq-cli-rsc.h 2023-01-06 11:52:32.000000000 +0100 @@ -791,20 +791,31 @@ RSC_TECH_L2_HW_PREFETCH, RSC_TECH_L2_HW_CL_PREFETCH, RSC_TECHNOLOGIES_SMM, + RSC_TECH_INTEL_SMM_COMM, + RSC_TECH_AMD_SMM_COMM, RSC_TECHNOLOGIES_HTT, RSC_TECHNOLOGIES_EIST, RSC_TECHNOLOGIES_IDA, RSC_TECHNOLOGIES_TURBO, RSC_TECHNOLOGIES_TBMT3, RSC_TECHNOLOGIES_VM, + RSC_TECH_INTEL_VMX_COMM, + RSC_TECH_AMD_SVM_COMM, RSC_TECHNOLOGIES_IOMMU, + RSC_TECH_INTEL_VTD_COMM, + RSC_TECH_AMD_V_COMM, RSC_TECHNOLOGIES_SMT, RSC_TECHNOLOGIES_CNQ, RSC_TECHNOLOGIES_CPB, + RSC_TECH_AMD_CPB_COMM, RSC_TECHNOLOGIES_EEO, + RSC_TECH_INTEL_EEO_COMM, RSC_TECHNOLOGIES_R2H, + RSC_TECH_INTEL_R2H_COMM, RSC_TECHNOLOGIES_HYPERV, RSC_TECHNOLOGIES_WDT, + RSC_TECH_INTEL_WDT_COMM, + RSC_TECH_AMD_WDT_COMM, RSC_TECH_HYPERV_NONE, RSC_TECH_BARE_METAL, RSC_TECH_HYPERV_XEN, @@ -814,6 +825,7 @@ RSC_TECH_HYPERV_VMWARE, RSC_TECH_HYPERV_HYPERV, RSC_PERF_MON_TITLE, + RSC_PERF_CAPS_TITLE, RSC_VERSION, RSC_COUNTERS, RSC_GENERAL_CTRS, @@ -1325,6 +1337,7 @@ RSC_MENU_ITEM_ISA_EXT, RSC_MENU_ITEM_TECH, RSC_MENU_ITEM_PERF_MON, + RSC_MENU_ITEM_PERF_CAPS, RSC_MENU_ITEM_POW_THERM, RSC_MENU_ITEM_CPUID, RSC_MENU_ITEM_SYS_REGS, diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-1.94.1/corefreq-cli.c new/CoreFreq-1.94.3/corefreq-cli.c --- old/CoreFreq-1.94.1/corefreq-cli.c 2023-01-03 08:10:54.000000000 +0100 +++ new/CoreFreq-1.94.3/corefreq-cli.c 2023-01-06 11:52:32.000000000 +0100 @@ -3475,7 +3475,7 @@ const unsigned short cond; const int tab; char *item; - const ASCII *code; + const ASCII *code, *comm; const CUINT spaces; const char *context; const unsigned long long shortkey; @@ -3486,7 +3486,7 @@ (unsigned int[]) { CRC_AMD, CRC_HYGON, 0 }, 0, 2, "%s%.*s", - RSC(TECHNOLOGIES_ICU).CODE(), + RSC(TECHNOLOGIES_ICU).CODE(), NULL, width - 3 - RSZ(TECHNOLOGIES_ICU), NULL, SCANKEY_NULL, @@ -3496,7 +3496,7 @@ (unsigned int[]) { CRC_AMD, CRC_HYGON, 0 }, RO(Shm)->Proc.Technology.L1_HW_IP_Prefetch, 3, "%s%.*sL1 HW IP <%3s>", - RSC(TECH_L1_HW_IP_PREFETCH).CODE(), + RSC(TECH_L1_HW_IP_PREFETCH).CODE(), NULL, width - (OutFunc ? 20 : 22) - RSZ(TECH_L1_HW_IP_PREFETCH), NULL, BOXKEY_L1_HW_IP_PREFETCH, @@ -3506,7 +3506,7 @@ (unsigned int[]) { CRC_INTEL, CRC_AMD, CRC_HYGON, 0 }, 0, 2, "%s%.*s", - RSC(TECHNOLOGIES_DCU).CODE(), + RSC(TECHNOLOGIES_DCU).CODE(), NULL, width - 3 - RSZ(TECHNOLOGIES_DCU), NULL, SCANKEY_NULL, @@ -3516,7 +3516,7 @@ (unsigned int[]) { CRC_INTEL, CRC_AMD, CRC_HYGON, 0 }, RO(Shm)->Proc.Technology.L1_HW_Prefetch, 3, "%s%.*sL1 HW <%3s>", - RSC(TECH_L1_HW_PREFETCH).CODE(), + RSC(TECH_L1_HW_PREFETCH).CODE(), NULL, width - (OutFunc ? 17 : 19) - RSZ(TECH_L1_HW_PREFETCH), NULL, BOXKEY_L1_HW_PREFETCH, @@ -3526,7 +3526,7 @@ (unsigned int[]) { CRC_INTEL, 0 }, RO(Shm)->Proc.Technology.L1_HW_IP_Prefetch, 3, "%s%.*sL1 HW IP <%3s>", - RSC(TECH_L1_HW_IP_PREFETCH).CODE(), + RSC(TECH_L1_HW_IP_PREFETCH).CODE(), NULL, width - (OutFunc ? 20 : 22) - RSZ(TECH_L1_HW_IP_PREFETCH), NULL, BOXKEY_L1_HW_IP_PREFETCH, @@ -3536,7 +3536,7 @@ (unsigned int[]) { CRC_INTEL, CRC_AMD, CRC_HYGON, 0 }, RO(Shm)->Proc.Technology.L2_HW_Prefetch, 3, "%s%.*sL2 HW <%3s>", - RSC(TECH_L2_HW_PREFETCH).CODE(), + RSC(TECH_L2_HW_PREFETCH).CODE(), NULL, width - (OutFunc ? 17 : 19) - RSZ(TECH_L2_HW_PREFETCH), NULL, BOXKEY_L2_HW_PREFETCH, @@ -3546,7 +3546,7 @@ (unsigned int[]) { CRC_INTEL, 0 }, RO(Shm)->Proc.Technology.L2_HW_CL_Prefetch, 3, "%s%.*sL2 HW CL <%3s>", - RSC(TECH_L2_HW_CL_PREFETCH).CODE(), + RSC(TECH_L2_HW_CL_PREFETCH).CODE(), NULL, width - (OutFunc ? 20 : 22) - RSZ(TECH_L2_HW_CL_PREFETCH), NULL, BOXKEY_L2_HW_CL_PREFETCH, @@ -3556,7 +3556,7 @@ (unsigned int[]) { CRC_INTEL, 0 }, RO(Shm)->Proc.Technology.SMM == 1, 2, "%s%.*sSMM-Dual [%3s]", - RSC(TECHNOLOGIES_SMM).CODE(), + RSC(TECHNOLOGIES_SMM).CODE(), RSC(TECH_INTEL_SMM_COMM).CODE(), width - 19 - RSZ(TECHNOLOGIES_SMM), NULL, SCANKEY_NULL, @@ -3566,7 +3566,7 @@ (unsigned int[]) { CRC_INTEL, 0 }, RO(Shm)->Proc.Features.HyperThreading == 1, 2, "%s%.*sHTT [%3s]", - RSC(TECHNOLOGIES_HTT).CODE(), + RSC(TECHNOLOGIES_HTT).CODE(), NULL, width - 14 - RSZ(TECHNOLOGIES_HTT), NULL, SCANKEY_NULL, @@ -3576,7 +3576,7 @@ (unsigned int[]) { CRC_INTEL, 0 }, RO(Shm)->Proc.Technology.EIST == 1, 2, "%s%.*sEIST <%3s>", - RSC(TECHNOLOGIES_EIST).CODE(), + RSC(TECHNOLOGIES_EIST).CODE(), NULL, width - 15 - RSZ(TECHNOLOGIES_EIST), NULL, BOXKEY_EIST, @@ -3586,7 +3586,7 @@ (unsigned int[]) { CRC_INTEL, 0 }, RO(Shm)->Proc.Features.Power.EAX.TurboIDA == 1, 2, "%s%.*sIDA [%3s]", - RSC(TECHNOLOGIES_IDA).CODE(), + RSC(TECHNOLOGIES_IDA).CODE(), NULL, width - 14 - RSZ(TECHNOLOGIES_IDA), NULL, SCANKEY_NULL, @@ -3598,6 +3598,7 @@ 2, "%s%.*sTURBO <%3s>", RO(Shm)->Proc.Features.Power.EAX.Turbo_V3 == 1 ? RSC(TECHNOLOGIES_TBMT3).CODE() : RSC(TECHNOLOGIES_TURBO).CODE(), + NULL, width - 16 - (RO(Shm)->Proc.Features.Power.EAX.Turbo_V3 == 1 ? RSZ(TECHNOLOGIES_TBMT3) : RSZ(TECHNOLOGIES_TURBO)), NULL, @@ -3608,7 +3609,7 @@ (unsigned int[]) { CRC_INTEL, 0 }, RO(Shm)->Proc.Features.EEO_Enable == 1, 2, "%s%.*sEEO <%3s>", - RSC(TECHNOLOGIES_EEO).CODE(), + RSC(TECHNOLOGIES_EEO).CODE(), RSC(TECH_INTEL_EEO_COMM).CODE(), width - 14 - RSZ(TECHNOLOGIES_EEO), NULL, BOXKEY_EEO, @@ -3618,7 +3619,7 @@ (unsigned int[]) { CRC_INTEL, 0 }, RO(Shm)->Proc.Features.R2H_Enable == 1, 2, "%s%.*sR2H <%3s>", - RSC(TECHNOLOGIES_R2H).CODE(), + RSC(TECHNOLOGIES_R2H).CODE(), RSC(TECH_INTEL_R2H_COMM).CODE(), width - 14 - RSZ(TECHNOLOGIES_R2H), NULL, BOXKEY_R2H, @@ -3628,7 +3629,7 @@ (unsigned int[]) { CRC_INTEL, 0 }, RO(Shm)->Proc.Technology.WDT == 1, 2, "%s%.*sTCO <%3s>", - RSC(TECHNOLOGIES_WDT).CODE(), + RSC(TECHNOLOGIES_WDT).CODE(), RSC(TECH_INTEL_WDT_COMM).CODE(), width - 14 - RSZ(TECHNOLOGIES_WDT), NULL, BOXKEY_WDT, @@ -3638,7 +3639,7 @@ (unsigned int[]) { CRC_INTEL, 0 }, RO(Shm)->Proc.Technology.VM == 1, 2, "%s%.*sVMX [%3s]", - RSC(TECHNOLOGIES_VM).CODE(), + RSC(TECHNOLOGIES_VM).CODE(), RSC(TECH_INTEL_VMX_COMM).CODE(), width - 14 - RSZ(TECHNOLOGIES_VM), NULL, SCANKEY_NULL, @@ -3648,7 +3649,7 @@ (unsigned int[]) { CRC_INTEL, 0 }, RO(Shm)->Proc.Technology.IOMMU == 1, 3, "%s%.*sVT-d [%3s]", - RSC(TECHNOLOGIES_IOMMU).CODE(), + RSC(TECHNOLOGIES_IOMMU).CODE(), RSC(TECH_INTEL_VTD_COMM).CODE(), width - (OutFunc ? 16 : 18) - RSZ(TECHNOLOGIES_IOMMU), NULL, SCANKEY_NULL, @@ -3658,7 +3659,7 @@ (unsigned int[]) { CRC_AMD, CRC_HYGON, 0 }, RO(Shm)->Proc.Technology.SMM == 1, 2, "%s%.*sSMM-Lock [%3s]", - RSC(TECHNOLOGIES_SMM).CODE(), + RSC(TECHNOLOGIES_SMM).CODE(), RSC(TECH_AMD_SMM_COMM).CODE(), width - 19 - RSZ(TECHNOLOGIES_SMM), NULL, SCANKEY_NULL, @@ -3668,7 +3669,7 @@ (unsigned int[]) { CRC_AMD, CRC_HYGON, 0 }, RO(Shm)->Proc.Features.HyperThreading == 1, 2, "%s%.*sSMT [%3s]", - RSC(TECHNOLOGIES_SMT).CODE(), + RSC(TECHNOLOGIES_SMT).CODE(), NULL, width - 14 - RSZ(TECHNOLOGIES_SMT), NULL, SCANKEY_NULL, @@ -3678,7 +3679,7 @@ (unsigned int[]) { CRC_AMD, CRC_HYGON, 0 }, RO(Shm)->Proc.PowerNow == 0b11, /* VID + FID */ 2, "%s%.*sCnQ [%3s]", - RSC(TECHNOLOGIES_CNQ).CODE(), + RSC(TECHNOLOGIES_CNQ).CODE(), NULL, width - 14 - RSZ(TECHNOLOGIES_CNQ), NULL, SCANKEY_NULL, @@ -3688,7 +3689,7 @@ (unsigned int[]) { CRC_AMD, CRC_HYGON, 0 }, RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Query.CStateBaseAddr != 0, 2, "%s%.*sCCx [%3s]", - RSC(PERF_MON_CORE_CSTATE).CODE(), + RSC(PERF_MON_CORE_CSTATE).CODE(), NULL, width - 14 - RSZ(PERF_MON_CORE_CSTATE), NULL, SCANKEY_NULL, @@ -3698,7 +3699,7 @@ (unsigned int[]) { CRC_AMD, CRC_HYGON, 0 }, RO(Shm)->Proc.Technology.Turbo == 1, 2, "%s%.*sCPB <%3s>", - RSC(TECHNOLOGIES_CPB).CODE(), + RSC(TECHNOLOGIES_CPB).CODE(), RSC(TECH_AMD_CPB_COMM).CODE(), width - 14 - RSZ(TECHNOLOGIES_CPB), NULL, BOXKEY_TURBO, @@ -3708,7 +3709,7 @@ (unsigned int[]) { CRC_AMD, CRC_HYGON, 0 }, RO(Shm)->Proc.Technology.WDT == 1, 2, "%s%.*sWDT <%3s>", - RSC(TECHNOLOGIES_WDT).CODE(), + RSC(TECHNOLOGIES_WDT).CODE(), RSC(TECH_AMD_WDT_COMM).CODE(), width - 14 - RSZ(TECHNOLOGIES_WDT), NULL, BOXKEY_WDT, @@ -3718,7 +3719,7 @@ (unsigned int[]) { CRC_AMD, CRC_HYGON, 0 }, RO(Shm)->Proc.Technology.VM == 1, 2, "%s%.*sSVM [%3s]", - RSC(TECHNOLOGIES_VM).CODE(), + RSC(TECHNOLOGIES_VM).CODE(), RSC(TECH_AMD_SVM_COMM).CODE(), width - 14 - RSZ(TECHNOLOGIES_VM), NULL, SCANKEY_NULL, @@ -3728,7 +3729,7 @@ (unsigned int[]) { CRC_AMD, CRC_HYGON, 0 }, RO(Shm)->Proc.Technology.IOMMU == 1, 3, "%s%.*sAMD-V [%3s]", - RSC(TECHNOLOGIES_IOMMU).CODE(), + RSC(TECHNOLOGIES_IOMMU).CODE(), RSC(TECH_AMD_V_COMM).CODE(), width - (OutFunc? 17 : 19) - RSZ(TECHNOLOGIES_IOMMU), NULL, SCANKEY_NULL, @@ -3740,7 +3741,7 @@ RO(Shm)->Proc.Technology.IOMMU_Ver_Major, RO(Shm)->Proc.Technology.IOMMU_Ver_Minor) > 0) & 0x0, 3, "%s%.*s"" [%12s]", - RSC(VERSION).CODE(), + RSC(VERSION).CODE(), NULL, width - (OutFunc? 21 : 23) - RSZ(VERSION), (RO(Shm)->Proc.Technology.IOMMU_Ver_Major > 0 || RO(Shm)->Proc.Technology.IOMMU_Ver_Minor > 0) ? @@ -3752,7 +3753,7 @@ NULL, RO(Shm)->Proc.Features.Std.ECX.Hyperv == 1, 3, "%s%.*s""%10s [%3s]", - RSC(TECHNOLOGIES_HYPERV).CODE(), + RSC(TECHNOLOGIES_HYPERV).CODE(), NULL, width - (OutFunc? 22 : 24) - RSZ(TECHNOLOGIES_HYPERV), (char*) Hypervisor[RO(Shm)->Proc.HypervisorID], SCANKEY_NULL, @@ -3762,7 +3763,7 @@ NULL, 0, 3, "%s%.*s"" [%12s]", - RSC(VENDOR_ID).CODE(), + RSC(VENDOR_ID).CODE(), NULL, width - (OutFunc? 21 : 23) - RSZ(VENDOR_ID), strlen(RO(Shm)->Proc.Features.Info.Hypervisor.ID) > 0 ? RO(Shm)->Proc.Features.Info.Hypervisor.ID @@ -3788,7 +3789,8 @@ } if (capable) { - TGrid *grid=PUT((TECH[idx].shortkey == SCANKEY_NULL) ? SCANKEY_NULL + TGrid *grid = \ + GridHover(PUT( (TECH[idx].shortkey == SCANKEY_NULL) ? SCANKEY_NULL : TECH[idx].shortkey, attrib[ TECH[idx].cond ], width, TECH[idx].tab, @@ -3796,7 +3798,7 @@ TECH[idx].spaces, hSpace, (TECH[idx].context == NULL) ? ENABLED(TECH[idx].cond) : TECH[idx].context, - ENABLED(TECH[idx].cond) ); + ENABLED(TECH[idx].cond) ), (char *)TECH[idx].comm); if (TECH[idx].Update != NULL) { @@ -4472,6 +4474,23 @@ RO(Shm)->Proc.Features.OSPM_CPC ? RSC(ENABLE).CODE() : RSC(MISSING).CODE() ); } + return reason; +} + +REASON_CODE SysInfoPerfCaps( Window *win, + CUINT width, + CELL_FUNC OutFunc, + unsigned int *cellPadding ) +{ + REASON_INIT(reason); + ATTRIBUTE *attrib[5] = { + RSC(SYSINFO_PERFMON_COND0).ATTR(), + RSC(SYSINFO_PERFMON_COND1).ATTR(), + RSC(SYSINFO_PERFMON_COND2).ATTR(), + RSC(SYSINFO_PERFMON_COND3).ATTR(), + RSC(SYSINFO_PERFMON_COND4).ATTR() + }; + unsigned int bix; bix = (RO(Shm)->Proc.Features.Power.EAX.HWP_Reg == 1) /* Intel:HWP */ || (RO(Shm)->Proc.Features.leaf80000008.EBX.CPPC == 1) /* AMD:CPPC */ || (RO(Shm)->Proc.Features.ACPI_CPPC == 1); /* ACPI:CPPC */ @@ -8024,7 +8043,7 @@ RSC(CREATE_MENU_DISABLE).ATTR()); #endif - StoreTCell(wMenu, SCANKEY_w, RSC(MENU_ITEM_POW_THERM).CODE(), + StoreTCell(wMenu, SCANKEY_z, RSC(MENU_ITEM_PERF_CAPS).CODE(), RSC(CREATE_MENU_SHORTKEY).ATTR()); /* Row 8 */ StoreTCell(wMenu, SCANKEY_SHIFT_e, RSC(MENU_ITEM_THEME).CODE(), @@ -8038,7 +8057,7 @@ RSC(CREATE_MENU_DISABLE).ATTR()); #endif - StoreTCell(wMenu, SCANKEY_u, RSC(MENU_ITEM_CPUID).CODE(), + StoreTCell(wMenu, SCANKEY_w, RSC(MENU_ITEM_POW_THERM).CODE(), RSC(CREATE_MENU_SHORTKEY).ATTR()); /* Row 9 */ StoreTCell(wMenu, SCANKEY_a, RSC(MENU_ITEM_ABOUT).CODE(), @@ -8052,8 +8071,8 @@ RSC(CREATE_MENU_DISABLE).ATTR()); #endif - StoreTCell(wMenu, SCANKEY_SHIFT_r, RSC(MENU_ITEM_SYS_REGS).CODE(), - RSC(CREATE_MENU_SHORTKEY).ATTR()); + StoreTCell(wMenu, SCANKEY_u, RSC(MENU_ITEM_CPUID).CODE(), + RSC(CREATE_MENU_SHORTKEY).ATTR()); /* Row 10 */ StoreTCell(wMenu, SCANKEY_h, RSC(MENU_ITEM_HELP).CODE(), RSC(CREATE_MENU_SHORTKEY).ATTR()); @@ -8066,10 +8085,8 @@ RSC(CREATE_MENU_DISABLE).ATTR()); #endif - StoreTCell(wMenu, SCANKEY_SHIFT_m, RSC(MENU_ITEM_MEM_CTRL).CODE(), - RO(Shm)->Uncore.CtrlCount > 0 ? - RSC(CREATE_MENU_SHORTKEY).ATTR() - : RSC(CREATE_MENU_DISABLE).ATTR()); + StoreTCell(wMenu, SCANKEY_SHIFT_r, RSC(MENU_ITEM_SYS_REGS).CODE(), + RSC(CREATE_MENU_SHORTKEY).ATTR()); /* Row 11 */ StoreTCell(wMenu, SCANKEY_CTRL_x, RSC(MENU_ITEM_QUIT).CODE(), RSC(CREATE_MENU_CTRL_KEY).ATTR()); @@ -8082,8 +8099,10 @@ RSC(CREATE_MENU_DISABLE).ATTR()); #endif - StoreTCell(wMenu, SCANKEY_SHIFT_h, RSC(MENU_ITEM_EVENTS).CODE(), - RSC(CREATE_MENU_SHORTKEY).ATTR()); + StoreTCell(wMenu, SCANKEY_SHIFT_m, RSC(MENU_ITEM_MEM_CTRL).CODE(), + RO(Shm)->Uncore.CtrlCount > 0 ? + RSC(CREATE_MENU_SHORTKEY).ATTR() + : RSC(CREATE_MENU_DISABLE).ATTR()); /* Row 12 */ StoreTCell(wMenu, SCANKEY_VOID, "", RSC(VOID).ATTR()); @@ -8095,7 +8114,8 @@ RSC(CREATE_MENU_DISABLE).ATTR()); #endif - StoreTCell(wMenu, SCANKEY_VOID, "", RSC(VOID).ATTR()); + StoreTCell(wMenu, SCANKEY_SHIFT_h, RSC(MENU_ITEM_EVENTS).CODE(), + RSC(CREATE_MENU_SHORTKEY).ATTR()); /* Row 13 */ StoreTCell(wMenu, SCANKEY_VOID, "", RSC(VOID).ATTR()); @@ -8825,6 +8845,20 @@ title = RSC(SMBIOS_TITLE).CODE(); } break; + case SCANKEY_z: + { + winOrigin.col = 5; + matrixSize.hth = CUMIN( Draw.Size.height - 5, + 2 + RO(Shm)->Proc.CPU.Count ); + #if defined(NO_UPPER) || defined(NO_LOWER) + winOrigin.row = 2; + #else + winOrigin.row = Draw.Area.MaxRows + TOP_HEADER_ROW; + #endif + SysInfoFunc = SysInfoPerfCaps; + title = RSC(PERF_CAPS_TITLE).CODE(); + } + break; } Window *wSysInfo = CreateWindow(wLayer, id, @@ -8853,6 +8887,7 @@ case SCANKEY_o: case SCANKEY_w: case SCANKEY_k: + case SCANKEY_z: StoreWindow(wSysInfo, .key.Enter, Enter_StickyCell); break; case SCANKEY_u: @@ -15599,6 +15634,7 @@ case SCANKEY_u: case SCANKEY_w: case SCANKEY_SHIFT_b: + case SCANKEY_z: { Window *win = SearchWinListById(scan->key, &winList); if (win == NULL) { @@ -20960,6 +20996,9 @@ if (IS_REASON_SUCCESSFUL(reason) == 0) { break; } } break; + case 'z': + reason = SysInfoPerfCaps(NULL, 80, NULL, NULL); + break; case 'j': JsonSysInfo(RO(Shm)); break; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-1.94.1/corefreqk.c new/CoreFreq-1.94.3/corefreqk.c --- old/CoreFreq-1.94.1/corefreqk.c 2023-01-03 08:10:54.000000000 +0100 +++ new/CoreFreq-1.94.3/corefreqk.c 2023-01-06 11:52:32.000000000 +0100 @@ -45,6 +45,10 @@ #ifdef CONFIG_AMD_NB #include <asm/amd_nb.h> #endif +#ifdef CONFIG_ACPI +#include <linux/acpi.h> +#include <acpi/processor.h> +#endif #ifdef CONFIG_ACPI_CPPC_LIB #include <acpi/cppc_acpi.h> #endif @@ -6608,14 +6612,28 @@ 1, MC_MAX_CHA, (const unsigned int[]) {PCI_DEVFN(0x18, 0x0)} ); - if ((PCI_CALLBACK) 0 == ret) { - unsigned short umc; - for (umc = 0; umc < PUBLIC(RO(Proc))->Uncore.CtrlCount; umc++) { - if (PUBLIC(RO(Proc))->Uncore.MC[umc].ChannelCount >= 2) { - PUBLIC(RO(Proc))->Uncore.MC[umc].ChannelCount >>= 1; - } + if ((PCI_CALLBACK) 0 == ret) { + unsigned short umc; + for (umc = 0; umc < PUBLIC(RO(Proc))->Uncore.CtrlCount; umc++) + { /* If UMC is quad channels (in 2 x 32-bits) then unpopulate odd channels*/ + if (PUBLIC(RO(Proc))->Uncore.MC[umc].ChannelCount >= 4) { + unsigned short cha; + for (cha=0; cha < PUBLIC(RO(Proc))->Uncore.MC[umc].ChannelCount; cha++) + { + if (cha & 1) { + unsigned short slot; + for(slot=0;slot < PUBLIC(RO(Proc))->Uncore.MC[umc].SlotCount;slot++) + { + const unsigned short chipselect_pair = slot << 1; + + BITCLR(LOCKLESS, PUBLIC(RO(Proc))->Uncore.MC[umc].Channel[cha]\ + .AMD17h.CHIP[chipselect_pair][0].Chip.value, 0); } + } } + } + } + } return ret; } @@ -18817,6 +18835,10 @@ { return Entry_AMD_F17h(pTimer, Call_SVI_RMB, 0, 2, 0LLU); } +static enum hrtimer_restart Cycle_AMD_Zen4_RPL(struct hrtimer *pTimer) +{ + return Entry_AMD_F17h(pTimer, Call_DFLT, 0, 0, 0LLU); +} static enum hrtimer_restart Cycle_AMD_F17h(struct hrtimer *pTimer) { return Entry_AMD_F17h(pTimer, Call_DFLT, 0, 0, 0LLU); @@ -18852,6 +18874,11 @@ smp_call_function_single(cpu, InitTimer, Cycle_AMD_Zen3Plus_RMB, 1); } +static void InitTimer_AMD_Zen4_RPL(unsigned int cpu) +{ + smp_call_function_single(cpu, InitTimer, Cycle_AMD_Zen4_RPL, 1); +} + static void Start_AMD_Family_17h(void *arg) { unsigned int cpu = smp_processor_id(); diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-1.94.1/corefreqk.h new/CoreFreq-1.94.3/corefreqk.h --- old/CoreFreq-1.94.1/corefreqk.h 2023-01-03 08:10:54.000000000 +0100 +++ new/CoreFreq-1.94.3/corefreqk.h 2023-01-06 11:52:32.000000000 +0100 @@ -1700,7 +1700,7 @@ static void CCD_AMD_Family_19h_Zen4_Temp(CORE_RO *Core) ; static void Query_AMD_F19h_61h_PerCluster(unsigned int cpu) ; -#define InitTimer_AMD_Zen4_RPL InitTimer_AMD_F19h_Zen3_SP +static void InitTimer_AMD_Zen4_RPL(unsigned int cpu) ; /* [Void] */ #define _Void_Signature {.ExtFamily=0x0, .Family=0x0, .ExtModel=0x0, .Model=0x0} @@ -5867,6 +5867,19 @@ }; static PROCESSOR_SPECIFIC AMD_Zen3_VMR_Specific[] = { { + .Brand = ZLIST("AMD Ryzen 7 5800X3D"), + .Boost = {+11, +1}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_VERMEER, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 1, + .UncoreUnlocked = 0, + .HSMP_Capable = 1, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\ + |LATCH_HSMP_CAPABLE + }, + { .Brand = ZLIST( "AMD Ryzen 5 5600X", \ "AMD Ryzen 7 5800X", "AMD Ryzen 5 5600" ), @@ -5934,19 +5947,6 @@ .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\ |LATCH_HSMP_CAPABLE }, - { - .Brand = ZLIST("5800X3D"), - .Boost = {+11, +1}, - .Param.Offset = {0, 0, 0}, - .CodeNameIdx = CN_VERMEER, - .TgtRatioUnlocked = 1, - .ClkRatioUnlocked = 0b10, - .TurboUnlocked = 0, - .UncoreUnlocked = 0, - .HSMP_Capable = 1, - .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\ - |LATCH_HSMP_CAPABLE - }, {0} }; static PROCESSOR_SPECIFIC AMD_Zen3_CZN_Specific[] = { @@ -6673,6 +6673,45 @@ }; static PROCESSOR_SPECIFIC AMD_Zen4_RPL_Specific[] = { { + .Brand = ZLIST("AMD Ryzen 9 7950X3D"), + .Boost = {+15, 0}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_RAPHAEL, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 1, + .UncoreUnlocked = 0, + .HSMP_Capable = 1, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\ + |LATCH_HSMP_CAPABLE + }, + { + .Brand = ZLIST("AMD Ryzen 9 7900X3D"), + .Boost = {+12, 0}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_RAPHAEL, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 1, + .UncoreUnlocked = 0, + .HSMP_Capable = 1, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\ + |LATCH_HSMP_CAPABLE + }, + { + .Brand = ZLIST("AMD Ryzen 7 7800X3D"), + .Boost = {+10, 0}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_RAPHAEL, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 1, + .UncoreUnlocked = 0, + .HSMP_Capable = 1, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\ + |LATCH_HSMP_CAPABLE + }, + { .Brand = ZLIST("AMD Ryzen 9 7950X"), .Boost = {+12, +1}, .Param.Offset = {0, 0, 0}, @@ -6705,6 +6744,45 @@ .Param.Offset = {0, 0, 0}, .CodeNameIdx = CN_RAPHAEL, .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 1, + .UncoreUnlocked = 0, + .HSMP_Capable = 1, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\ + |LATCH_HSMP_CAPABLE + }, + { + .Brand = ZLIST("AMD Ryzen 9 7900"), + .Boost = {+16, +1}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_RAPHAEL, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 1, + .UncoreUnlocked = 0, + .HSMP_Capable = 1, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\ + |LATCH_HSMP_CAPABLE + }, + { + .Brand = ZLIST("AMD Ryzen 7 7700"), + .Boost = {+14, +1}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_RAPHAEL, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 1, + .UncoreUnlocked = 0, + .HSMP_Capable = 1, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\ + |LATCH_HSMP_CAPABLE + }, + { + .Brand = ZLIST("AMD Ryzen 5 7600"), + .Boost = {+12, +1}, + .Param.Offset = {0, 0, 0}, + .CodeNameIdx = CN_RAPHAEL, + .TgtRatioUnlocked = 1, .ClkRatioUnlocked = 0b10, .TurboUnlocked = 1, .UncoreUnlocked = 0, diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-1.94.1/coretypes.h new/CoreFreq-1.94.3/coretypes.h --- old/CoreFreq-1.94.1/coretypes.h 2023-01-03 08:10:54.000000000 +0100 +++ new/CoreFreq-1.94.3/coretypes.h 2023-01-06 11:52:32.000000000 +0100 @@ -6,7 +6,7 @@ #define COREFREQ_MAJOR 1 #define COREFREQ_MINOR 94 -#define COREFREQ_REV 1 +#define COREFREQ_REV 3 #if !defined(CORE_COUNT) #define CORE_COUNT 256
