Script 'mail_helper' called by obssrc
Hello community,
here is the log from the commit of package CoreFreq for openSUSE:Factory
checked in at 2023-02-10 14:35:51
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Comparing /work/SRC/openSUSE:Factory/CoreFreq (Old)
and /work/SRC/openSUSE:Factory/.CoreFreq.new.1848 (New)
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "CoreFreq"
Fri Feb 10 14:35:51 2023 rev:22 rq:1064171 version:1.95.2
Changes:
--------
--- /work/SRC/openSUSE:Factory/CoreFreq/CoreFreq.changes 2023-01-23
18:32:49.980421172 +0100
+++ /work/SRC/openSUSE:Factory/.CoreFreq.new.1848/CoreFreq.changes
2023-02-10 14:35:52.414118877 +0100
@@ -1,0 +2,20 @@
+Thu Feb 9 16:49:17 UTC 2023 - Dirk Müller <dmuel...@suse.com>
+
+- update to 1.95.2:
+ * Fixed the aggregation of the minimum ratio
+ Intel:
+ * [Airmont][Silvermont] Attempt to decode `tCKE` from DRMC
+ register
+ * [Airmont] Improve `tWTPr`, `B2B`, `tWWDR` timings
+ * [Airmont] Provide a new IMC decoder
+ * Add the Emerald Rapids architecture entry
+ * [DDR5][DDR4] Add the `RCDw` IMC timing
+ * [Raptor Lake ] De-activate the MSR Uncore counter
+ AMD:
+ * "Zen3/Barcelo-R" and "Zen3+ Rembrandt-R" codenames
+ * [Zen] Thermal highest limit reset fix
+ Misc:
+ * Code review and Registers documentation:
+ AMD HWCR, Intel HDC and DRP
+
+-------------------------------------------------------------------
Old:
----
CoreFreq-1.95.1.tar.gz
New:
----
CoreFreq-1.95.2.tar.gz
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Other differences:
------------------
++++++ CoreFreq.spec ++++++
--- /var/tmp/diff_new_pack.geUit0/_old 2023-02-10 14:35:52.802121196 +0100
+++ /var/tmp/diff_new_pack.geUit0/_new 2023-02-10 14:35:52.814121267 +0100
@@ -17,7 +17,7 @@
Name: CoreFreq
-Version: 1.95.1
+Version: 1.95.2
Release: 0
Summary: CPU monitoring software for 64-bit processors
License: GPL-2.0-or-later
++++++ CoreFreq-1.95.1.tar.gz -> CoreFreq-1.95.2.tar.gz ++++++
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.95.1/Makefile new/CoreFreq-1.95.2/Makefile
--- old/CoreFreq-1.95.1/Makefile 2023-01-23 00:29:55.000000000 +0100
+++ new/CoreFreq-1.95.2/Makefile 2023-02-05 15:34:56.000000000 +0100
@@ -219,6 +219,7 @@
"| | MSR_IA32_APERF | MSR_IA32_MPERF | |\n"\
"| | MSR_CORE_PERF_FIXED_CTR1 | MSR_CORE_PERF_FIXED_CTR2 | |\n"\
"| | MSR_PPERF | MSR_PPERF | |\n"\
+ "| | | MSR_ANY_CORE_C0 | |\n"\
"| | MSR_AMD_F17H_APERF | MSR_AMD_F17H_MPERF | |\n"\
"| ------------------------------------------------------- |\n"\
"| |\n"\
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.95.1/amd_reg.h
new/CoreFreq-1.95.2/amd_reg.h
--- old/CoreFreq-1.95.1/amd_reg.h 2023-01-23 00:29:55.000000000 +0100
+++ new/CoreFreq-1.95.2/amd_reg.h 2023-02-05 15:34:56.000000000 +0100
@@ -351,8 +351,10 @@
IRPerfEn : 31-30, /* RW: Enable Instructions Retired counter */
SmmBaseLock : 32-31, /* MSR SMM_BASE saved/restored from save area*/
TprLoweringDis : 33-32, /* RW: FastTprLoweringDis: 1=Disabled */
- SmmPgCfgLock : 34-33,
- Reserved8 : 64-34;
+ SmmPgCfgLock : 34-33, /* SMM reserved and iff 8000_0021_EAX[3] */
+ Reserved8 : 35-34,
+ CpuidUserDis : 36-35, /* CPUID User Disable iff 8000_0021_EAX[17] */
+ Reserved9 : 64-36;
} Family_17h;
struct
{
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.95.1/corefreq-api.h
new/CoreFreq-1.95.2/corefreq-api.h
--- old/CoreFreq-1.95.1/corefreq-api.h 2023-01-23 00:29:55.000000000 +0100
+++ new/CoreFreq-1.95.2/corefreq-api.h 2023-02-05 15:34:56.000000000 +0100
@@ -679,6 +679,7 @@
/* 0F00h */ SOC_MC_DTR2 DTR2; /* 32 bits */
/* 0F00h */ SOC_MC_DTR3 DTR3; /* 32 bits */
/* 0F00h */ SOC_MC_DRFC DRFC; /* 32 bits */
+ SOC_MC_DRMC DRMC; /* 32 bits */
/* 0F00h */ SOC_MC_BIOS_CFG BIOS_CFG; /* 32 bits */
} SLM;
struct {
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.95.1/corefreq-cli-rsc-en.h
new/CoreFreq-1.95.2/corefreq-cli-rsc-en.h
--- old/CoreFreq-1.95.1/corefreq-cli-rsc-en.h 2023-01-23 00:29:55.000000000
+0100
+++ new/CoreFreq-1.95.2/corefreq-cli-rsc-en.h 2023-02-05 15:34:56.000000000
+0100
@@ -1421,6 +1421,8 @@
#define RSC_DDR3_CKE_COMM_CODE_EN " tCKE ( ClocK Enable ) "
#define RSC_DDR3_ECC_COMM_CODE_EN " ECC ( Error Correcting Code ) "
+#define RSC_DDR4_RCD_R_COMM_CODE_EN " tRCD_R ( Activate to Read CAS ) "
+#define RSC_DDR4_RCD_W_COMM_CODE_EN " tRCD_W ( Activate to Write CAS ) "
#define RSC_DDR4_RDRD_SCL_COMM_CODE_EN " tRDRD ( Read to Read, Same Bank ) "
#define RSC_DDR4_RDRD_SC_COMM_CODE_EN " tRDRD ( Read to Read, Different Bank )
"
#define RSC_DDR4_RDRD_SD_COMM_CODE_EN " tRDRD ( Read to Read, Different Rank )
"
@@ -1467,8 +1469,6 @@
#define RSC_DDR4_CPDED_COMM_CODE_EN " tCPDED ( Command Pass Disable Delay ) "
#define RSC_DDR4_GEAR_COMM_CODE_EN " GEAR ( Clock Gear Mode ) "
-#define RSC_DDR4_ZEN_RCD_R_COMM_CODE_EN " tRCD_R ( Activate to Read CAS ) "
-#define RSC_DDR4_ZEN_RCD_W_COMM_CODE_EN " tRCD_W ( Activate to Write CAS ) "
#define RSC_DDR4_ZEN_RC_COMM_CODE_EN " tRC ( Activate to Activate ) "
#define RSC_DDR4_ZEN_WTR_S_COMM_CODE_EN \
@@ -2399,7 +2399,8 @@
#define RSC_DDR3_ECC_CODE " ECC"
#define RSC_DDR4_CL_CODE " CL"
-#define RSC_DDR4_RCD_CODE " RCD"
+#define RSC_DDR4_RCD_R_CODE " RCDr"
+#define RSC_DDR4_RCD_W_CODE " RCDw"
#define RSC_DDR4_RP_CODE " RP"
#define RSC_DDR4_RAS_CODE " RAS"
#define RSC_DDR4_RRD_CODE " RRD"
@@ -2410,7 +2411,7 @@
#define RSC_DDR4_FAW_CODE " FAW"
#define RSC_DDR4_GEAR_CODE " GEAR"
#define RSC_DDR4_CWL_CODE " CWL"
-#define RSC_DDR4_CMD_CODE " CMD "
+#define RSC_DDR4_CMD_CODE " CMD"
#define RSC_DDR4_REFI_CODE " REFI"
#define RSC_DDR4_RDRD_SCL_CODE " sgRR"
#define RSC_DDR4_RDRD_SC_CODE " dgRR"
@@ -2430,13 +2431,11 @@
#define RSC_DDR4_WRWR_DD_CODE " ddWW"
#define RSC_DDR4_RRD_S_CODE " RRDs"
#define RSC_DDR4_RRD_L_CODE " RRDl"
-#define RSC_DDR4_CKE_CODE " CKE "
+#define RSC_DDR4_CKE_CODE " CKE"
#define RSC_DDR4_CPDED_CODE "CPDED"
#define RSC_DDR4_ECC_CODE " ECC"
#define RSC_DDR4_ZEN_CL_CODE " CL "
-#define RSC_DDR4_ZEN_RCD_R_CODE " RCDr"
-#define RSC_DDR4_ZEN_RCD_W_CODE " RCDw"
#define RSC_DDR4_ZEN_RP_CODE " RP "
#define RSC_DDR4_ZEN_RAS_CODE " RAS "
#define RSC_DDR4_ZEN_RC_CODE " RC "
@@ -2470,8 +2469,6 @@
#define RSC_DDR4_ZEN_BGS_ALT_CODE ":Alt "
#define RSC_DDR4_ZEN_BAN_CODE " Ban "
#define RSC_DDR4_ZEN_RCPAGE_CODE " Page"
-#define RSC_DDR4_ZEN_CKE_CODE " CKE"
-#define RSC_DDR4_ZEN_CMD_CODE " CMD"
#define RSC_DDR4_ZEN_GDM_CODE " GDM"
#define RSC_DDR4_ZEN_ECC_CODE " ECC"
#define RSC_DDR4_ZEN_MRD_CODE " MRD:"
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.95.1/corefreq-cli-rsc-fr.h
new/CoreFreq-1.95.2/corefreq-cli-rsc-fr.h
--- old/CoreFreq-1.95.1/corefreq-cli-rsc-fr.h 2023-01-23 00:29:55.000000000
+0100
+++ new/CoreFreq-1.95.2/corefreq-cli-rsc-fr.h 2023-02-05 15:34:56.000000000
+0100
@@ -879,6 +879,8 @@
#define RSC_DDR3_CKE_COMM_CODE_FR RSC_DDR3_CKE_COMM_CODE_EN
#define RSC_DDR3_ECC_COMM_CODE_FR RSC_DDR3_ECC_COMM_CODE_EN
+#define RSC_DDR4_RCD_R_COMM_CODE_FR RSC_DDR4_RCD_R_COMM_CODE_EN
+#define RSC_DDR4_RCD_W_COMM_CODE_FR RSC_DDR4_RCD_W_COMM_CODE_EN
#define RSC_DDR4_RDRD_SCL_COMM_CODE_FR RSC_DDR4_RDRD_SCL_COMM_CODE_EN
#define RSC_DDR4_RDRD_SC_COMM_CODE_FR RSC_DDR4_RDRD_SC_COMM_CODE_EN
#define RSC_DDR4_RDRD_SD_COMM_CODE_FR RSC_DDR4_RDRD_SD_COMM_CODE_EN
@@ -900,8 +902,6 @@
#define RSC_DDR4_CPDED_COMM_CODE_FR RSC_DDR4_CPDED_COMM_CODE_EN
#define RSC_DDR4_GEAR_COMM_CODE_FR RSC_DDR4_GEAR_COMM_CODE_EN
-#define RSC_DDR4_ZEN_RCD_R_COMM_CODE_FR RSC_DDR4_ZEN_RCD_R_COMM_CODE_EN
-#define RSC_DDR4_ZEN_RCD_W_COMM_CODE_FR RSC_DDR4_ZEN_RCD_W_COMM_CODE_EN
#define RSC_DDR4_ZEN_RC_COMM_CODE_FR RSC_DDR4_ZEN_RC_COMM_CODE_EN
#define RSC_DDR4_ZEN_WTR_S_COMM_CODE_FR RSC_DDR4_ZEN_WTR_S_COMM_CODE_EN
#define RSC_DDR4_ZEN_WTR_L_COMM_CODE_FR RSC_DDR4_ZEN_WTR_L_COMM_CODE_EN
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.95.1/corefreq-cli-rsc.c
new/CoreFreq-1.95.2/corefreq-cli-rsc.c
--- old/CoreFreq-1.95.1/corefreq-cli-rsc.c 2023-01-23 00:29:55.000000000
+0100
+++ new/CoreFreq-1.95.2/corefreq-cli-rsc.c 2023-02-05 15:34:56.000000000
+0100
@@ -1330,7 +1330,8 @@
LDQ(RSC_DDR3_CKE),
LDQ(RSC_DDR3_ECC),
LDQ(RSC_DDR4_CL),
- LDQ(RSC_DDR4_RCD),
+ LDQ(RSC_DDR4_RCD_R),
+ LDQ(RSC_DDR4_RCD_W),
LDQ(RSC_DDR4_RP),
LDQ(RSC_DDR4_RAS),
LDQ(RSC_DDR4_RRD),
@@ -1365,8 +1366,6 @@
LDQ(RSC_DDR4_CPDED),
LDQ(RSC_DDR4_ECC),
LDQ(RSC_DDR4_ZEN_CL),
- LDQ(RSC_DDR4_ZEN_RCD_R),
- LDQ(RSC_DDR4_ZEN_RCD_W),
LDQ(RSC_DDR4_ZEN_RP),
LDQ(RSC_DDR4_ZEN_RAS),
LDQ(RSC_DDR4_ZEN_RC),
@@ -1400,8 +1399,6 @@
LDQ(RSC_DDR4_ZEN_BGS_ALT),
LDQ(RSC_DDR4_ZEN_BAN),
LDQ(RSC_DDR4_ZEN_RCPAGE),
- LDQ(RSC_DDR4_ZEN_CKE),
- LDQ(RSC_DDR4_ZEN_CMD),
LDQ(RSC_DDR4_ZEN_GDM),
LDQ(RSC_DDR4_ZEN_ECC),
LDQ(RSC_DDR4_ZEN_MRD),
@@ -1449,6 +1446,8 @@
LDT(RSC_DDR3_XP_COMM),
LDT(RSC_DDR3_CKE_COMM),
LDT(RSC_DDR3_ECC_COMM),
+ LDT(RSC_DDR4_RCD_R_COMM),
+ LDT(RSC_DDR4_RCD_W_COMM),
LDT(RSC_DDR4_RDRD_SCL_COMM),
LDT(RSC_DDR4_RDRD_SC_COMM),
LDT(RSC_DDR4_RDRD_SD_COMM),
@@ -1469,8 +1468,6 @@
LDT(RSC_DDR4_RRD_L_COMM),
LDT(RSC_DDR4_CPDED_COMM),
LDT(RSC_DDR4_GEAR_COMM),
- LDT(RSC_DDR4_ZEN_RCD_R_COMM),
- LDT(RSC_DDR4_ZEN_RCD_W_COMM),
LDT(RSC_DDR4_ZEN_RC_COMM),
LDT(RSC_DDR4_ZEN_WTR_S_COMM),
LDT(RSC_DDR4_ZEN_WTR_L_COMM),
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.95.1/corefreq-cli-rsc.h
new/CoreFreq-1.95.2/corefreq-cli-rsc.h
--- old/CoreFreq-1.95.1/corefreq-cli-rsc.h 2023-01-23 00:29:55.000000000
+0100
+++ new/CoreFreq-1.95.2/corefreq-cli-rsc.h 2023-02-05 15:34:56.000000000
+0100
@@ -1133,7 +1133,8 @@
RSC_DDR3_CKE,
RSC_DDR3_ECC,
RSC_DDR4_CL,
- RSC_DDR4_RCD,
+ RSC_DDR4_RCD_R,
+ RSC_DDR4_RCD_W,
RSC_DDR4_RP,
RSC_DDR4_RAS,
RSC_DDR4_RRD,
@@ -1168,8 +1169,6 @@
RSC_DDR4_CPDED,
RSC_DDR4_ECC,
RSC_DDR4_ZEN_CL,
- RSC_DDR4_ZEN_RCD_R,
- RSC_DDR4_ZEN_RCD_W,
RSC_DDR4_ZEN_RP,
RSC_DDR4_ZEN_RAS,
RSC_DDR4_ZEN_RC,
@@ -1203,8 +1202,6 @@
RSC_DDR4_ZEN_BGS_ALT,
RSC_DDR4_ZEN_BAN,
RSC_DDR4_ZEN_RCPAGE,
- RSC_DDR4_ZEN_CKE,
- RSC_DDR4_ZEN_CMD,
RSC_DDR4_ZEN_GDM,
RSC_DDR4_ZEN_ECC,
RSC_DDR4_ZEN_MRD,
@@ -1252,6 +1249,8 @@
RSC_DDR3_XP_COMM,
RSC_DDR3_CKE_COMM,
RSC_DDR3_ECC_COMM,
+ RSC_DDR4_RCD_R_COMM,
+ RSC_DDR4_RCD_W_COMM,
RSC_DDR4_RDRD_SCL_COMM,
RSC_DDR4_RDRD_SC_COMM,
RSC_DDR4_RDRD_SD_COMM,
@@ -1272,8 +1271,6 @@
RSC_DDR4_RRD_L_COMM,
RSC_DDR4_CPDED_COMM,
RSC_DDR4_GEAR_COMM,
- RSC_DDR4_ZEN_RCD_R_COMM,
- RSC_DDR4_ZEN_RCD_W_COMM,
RSC_DDR4_ZEN_RC_COMM,
RSC_DDR4_ZEN_WTR_S_COMM,
RSC_DDR4_ZEN_WTR_L_COMM,
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.95.1/corefreq-cli.c
new/CoreFreq-1.95.2/corefreq-cli.c
--- old/CoreFreq-1.95.1/corefreq-cli.c 2023-01-23 00:29:55.000000000 +0100
+++ new/CoreFreq-1.95.2/corefreq-cli.c 2023-02-05 15:34:56.000000000 +0100
@@ -169,15 +169,21 @@
const unsigned int highestFactory = MAXCLOCK_TO_RATIO(
unsigned int, RO(Shm)->Proc.Features.Factory.Clock.Hz
);
- enum RATIO_BOOST lt, rt;
+ enum RATIO_BOOST lt, rt, min_boost = BOOST(MIN);
+ if ((RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Boost[BOOST(HWP_MIN)] > 0)
+ && (RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Boost[BOOST(HWP_MIN)]
+ < RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Boost[BOOST(MIN)]))
+ {
+ min_boost = BOOST(HWP_MIN);
+ }
unsigned int cpu,
lowest = RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Boost[BOOST(MAX)],
- highest = RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Boost[BOOST(MIN)];
+ highest = RO(Shm)->Cpu[RO(Shm)->Proc.Service.Core].Boost[min_boost];
Ruler.Count = 0;
- SetTopOfRuler(RO(Shm)->Proc.Service.Core, BOOST(MIN));
+ SetTopOfRuler(RO(Shm)->Proc.Service.Core, min_boost);
- lt = BOOST(MIN);
+ lt = min_boost;
while (lt < BOOST(SIZE))
{
Ruler.Top[lt] = RO(Shm)->Proc.Service.Core;
@@ -193,7 +199,7 @@
{
SetTopOftheTop(cpu, lt, &lowest, & highest);
- for (rt = BOOST(MIN); rt < Ruler.Count; rt++)
+ for (rt = min_boost; rt < Ruler.Count; rt++)
{
if (Ruler.Uniq[rt] == RO(Shm)->Cpu[cpu].Boost[lt])
{
@@ -208,7 +214,7 @@
}
lt = lt + 1;
}
- InsertionSortRuler(Ruler.Uniq, Ruler.Count, BOOST(MIN));
+ InsertionSortRuler(Ruler.Uniq, Ruler.Count, min_boost);
Ruler.Minimum = (double) lowest;
Ruler.Maximum = (double) highest;
@@ -7035,7 +7041,8 @@
{
RSC(MEM_CTRL_CHANNEL).CODE(),
RSC(DDR4_CL).CODE(),
- RSC(DDR4_RCD).CODE(),
+ RSC(DDR4_RCD_R).CODE(),
+ RSC(DDR4_RCD_W).CODE(),
RSC(DDR4_RP).CODE(),
RSC(DDR4_RAS).CODE(),
RSC(DDR4_RRD_S).CODE(),
@@ -7046,8 +7053,7 @@
RSC(DDR4_WTP).CODE(),
RSC(DDR4_CWL).CODE(),
RSC(DDR4_CKE).CODE(),
- RSC(DDR4_CMD).CODE(),
- RSC(DDR4_GEAR).CODE()
+ RSC(DDR4_CMD).CODE()
},
{
RSC(MEM_CTRL_MTY_CELL).CODE(),
@@ -7075,12 +7081,12 @@
RSC(MEM_CTRL_MTY_CELL).CODE(),
RSC(MEM_CTRL_MTY_CELL).CODE(),
RSC(MEM_CTRL_MTY_CELL).CODE(),
- RSC(MEM_CTRL_MTY_CELL).CODE(),
RSC(DDR4_REFI).CODE(),
RSC(DDR4_RFC).CODE(),
RSC(DDR3_XS).CODE(),
RSC(DDR3_XP).CODE(),
RSC(DDR4_CPDED).CODE(),
+ RSC(DDR4_GEAR).CODE(),
RSC(DDR4_ECC).CODE()
}
};
@@ -7088,7 +7094,8 @@
{
NULL,
RSC(DDR3_CL_COMM).CODE(),
- RSC(DDR3_RCD_COMM).CODE(),
+ RSC(DDR4_RCD_R_COMM).CODE(),
+ RSC(DDR4_RCD_W_COMM).CODE(),
RSC(DDR3_RP_COMM).CODE(),
RSC(DDR3_RAS_COMM).CODE(),
RSC(DDR4_RRD_S_COMM).CODE(),
@@ -7099,8 +7106,7 @@
RSC(DDR3_WTP_COMM).CODE(),
RSC(DDR3_CWL_COMM).CODE(),
RSC(DDR3_CKE_COMM).CODE(),
- RSC(DDR3_CMD_COMM).CODE(),
- RSC(DDR4_GEAR_COMM).CODE()
+ RSC(DDR3_CMD_COMM).CODE()
},
{
NULL,
@@ -7128,12 +7134,12 @@
NULL,
NULL,
NULL,
- NULL,
RSC(DDR3_REFI_COMM).CODE(),
RSC(DDR3_RFC_COMM).CODE(),
RSC(DDR3_XS_COMM).CODE(),
RSC(DDR3_XP_COMM).CODE(),
RSC(DDR4_CPDED_COMM).CODE(),
+ RSC(DDR4_GEAR_COMM).CODE(),
RSC(DDR3_ECC_COMM).CODE()
}
};
@@ -7153,7 +7159,8 @@
PRT(IMC, attrib[0], "\x20\x20#%-2u", cha);
PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tCL);
- PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRCD);
+ PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRCD_RD);
+ PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRCD_WR);
PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRP);
PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRAS);
PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRRDS);
@@ -7163,9 +7170,8 @@
PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tRTPr);
PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tWTPr);
PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tCWL);
- PRT(IMC, attrib[1], "%4u\x20", TIMING(mc, cha).tCKE);
- PRT(IMC, attrib[1], "%3uT\x20", TIMING(mc, cha).CMD_Rate);
- PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).GEAR);
+ PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tCKE);
+ PRT(IMC, attrib[1], "\x20%3uT", TIMING(mc, cha).CMD_Rate);
}
for (nc = 0; nc < MC_MATX; nc++) {
GridHover( PRT(IMC, attrib[0], Header_DDR4[1][nc]),
@@ -7209,7 +7215,7 @@
PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tWRWR_DR);
PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tWRWR_DD);
- for (nc = 0; nc < (MC_MATX - 12); nc++) {
+ for (nc = 0; nc < (MC_MATX - 13); nc++) {
PRT(IMC, attrib[0], MEM_CTRL_FMT, MC_MATY, HSPACE);
}
@@ -7221,6 +7227,7 @@
PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tXS);
PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tXP);
PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).tCPDED);
+ PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).GEAR);
PRT(IMC, attrib[1], "%5u", TIMING(mc, cha).ECC);
}
}
@@ -7235,8 +7242,8 @@
{
RSC(MEM_CTRL_CHANNEL).CODE(),
RSC(DDR4_ZEN_CL).CODE(),
- RSC(DDR4_ZEN_RCD_R).CODE(),
- RSC(DDR4_ZEN_RCD_W).CODE(),
+ RSC(DDR4_RCD_R).CODE(),
+ RSC(DDR4_RCD_W).CODE(),
RSC(DDR4_ZEN_RP).CODE(),
RSC(DDR4_ZEN_RAS).CODE(),
RSC(DDR4_ZEN_RC).CODE(),
@@ -7286,8 +7293,8 @@
RSC(DDR4_ZEN_BGS_ALT).CODE(),
RSC(DDR4_ZEN_BAN).CODE(),
RSC(DDR4_ZEN_RCPAGE).CODE(),
- RSC(DDR4_ZEN_CKE).CODE(),
- RSC(DDR4_ZEN_CMD).CODE(),
+ RSC(DDR4_CKE).CODE(),
+ RSC(DDR4_CMD).CODE(),
RSC(DDR4_ZEN_GDM).CODE(),
RSC(DDR4_ZEN_ECC).CODE()
},
@@ -7313,8 +7320,8 @@
{
NULL,
RSC(DDR3_CL_COMM).CODE(),
- RSC(DDR4_ZEN_RCD_R_COMM).CODE(),
- RSC(DDR4_ZEN_RCD_W_COMM).CODE(),
+ RSC(DDR4_RCD_R_COMM).CODE(),
+ RSC(DDR4_RCD_W_COMM).CODE(),
RSC(DDR3_RP_COMM).CODE(),
RSC(DDR3_RAS_COMM).CODE(),
RSC(DDR4_ZEN_RC_COMM).CODE(),
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.95.1/corefreqd.c
new/CoreFreq-1.95.2/corefreqd.c
--- old/CoreFreq-1.95.1/corefreqd.c 2023-01-23 00:29:55.000000000 +0100
+++ new/CoreFreq-1.95.2/corefreqd.c 2023-02-05 15:34:56.000000000 +0100
@@ -3043,20 +3043,15 @@
for (cha = 0; cha < RO(Shm)->Uncore.MC[mc].ChannelCount; cha++)
{
/* Standard Timings */
- TIMING(mc, cha).tCL = \
- RO(Proc)->Uncore.MC[mc].SLM.DTR0.tCL + 5;
+ TIMING(mc, cha).tCL = RO(Proc)->Uncore.MC[mc].SLM.DTR0.tCL + 5;
- TIMING(mc, cha).tRCD = \
- RO(Proc)->Uncore.MC[mc].SLM.DTR0.tRCD + 5;
+ TIMING(mc, cha).tRCD = RO(Proc)->Uncore.MC[mc].SLM.DTR0.tRCD + 5;
- TIMING(mc, cha).tRP = \
- RO(Proc)->Uncore.MC[mc].SLM.DTR0.tRP + 5;
+ TIMING(mc, cha).tRP = RO(Proc)->Uncore.MC[mc].SLM.DTR0.tRP + 5;
- TIMING(mc, cha).tRAS = \
- RO(Proc)->Uncore.MC[mc].SLM.DTR1.tRAS;
+ TIMING(mc, cha).tRAS = RO(Proc)->Uncore.MC[mc].SLM.DTR1.tRAS;
- TIMING(mc, cha).tRRD = \
- RO(Proc)->Uncore.MC[mc].SLM.DTR1.tRRD + 4;
+ TIMING(mc, cha).tRRD = RO(Proc)->Uncore.MC[mc].SLM.DTR1.tRRD + 4;
TIMING(mc, cha).tRFC = \
RO(Proc)->Uncore.MC[mc].SLM.DTR0.tXS == 0 ? 256 : 384;
@@ -3075,18 +3070,13 @@
TIMING(mc, cha).tREFI *= RO(Shm)->Uncore.CtrlSpeed;
TIMING(mc, cha).tREFI /= 20;
-/*TODO( Advanced Timings )
- TIMING(mc, cha).tCKE = \
- RO(Proc)->Uncore.MC[mc].Channel[cha].SLM
-*/
- TIMING(mc, cha).tRTPr = \
- RO(Proc)->Uncore.MC[mc].SLM.DTR1.tRTP + 4;
+ TIMING(mc, cha).tCKE = RO(Proc)->Uncore.MC[mc].SLM.DRMC.CKEVAL;
- TIMING(mc, cha).tWTPr = \
- RO(Proc)->Uncore.MC[mc].SLM.DTR1.tWTP + 14;
+ TIMING(mc, cha).tRTPr = RO(Proc)->Uncore.MC[mc].SLM.DTR1.tRTP + 4;
- TIMING(mc, cha).B2B = \
- RO(Proc)->Uncore.MC[mc].SLM.DTR1.tCCD;
+ TIMING(mc, cha).tWTPr = RO(Proc)->Uncore.MC[mc].SLM.DTR1.tWTP + 14;
+
+ TIMING(mc, cha).B2B = RO(Proc)->Uncore.MC[mc].SLM.DTR1.tCCD;
switch (RO(Proc)->Uncore.MC[mc].SLM.DTR1.tFAW) {
case 0 ... 1:
@@ -3098,64 +3088,50 @@
break;
}
- TIMING(mc, cha).tCWL = \
- RO(Proc)->Uncore.MC[mc].SLM.DTR1.tWCL + 3;
-/* Same Rank */
-/*TODO( Read to Read )
- TIMING(mc, cha).tsrRdTRd = \
- RO(Proc)->Uncore.MC[mc].SLM.DTR?.;
+ TIMING(mc, cha).tCWL = RO(Proc)->Uncore.MC[mc].SLM.DTR1.tWCL + 3;
+
+/*TODO( Read to Read. Same Rank )
+ TIMING(mc, cha).tsrRdTRd = RO(Proc)->Uncore.MC[mc].SLM.DTR?.;
*/
- TIMING(mc, cha).tsrRdTWr = 6
- + RO(Proc)->Uncore.MC[mc].SLM.DTR3.tRWSR;
+ TIMING(mc, cha).tsrRdTWr = 6 + RO(Proc)->Uncore.MC[mc].SLM.DTR3.tRWSR;
- TIMING(mc, cha).tsrWrTRd = 11
- + RO(Proc)->Uncore.MC[mc].SLM.DTR3.tWRSR;
-/*TODO( Write to Write )
- TIMING(mc, cha).tsrWrTWr = \
- RO(Proc)->Uncore.MC[mc].Channel[cha].SLM.DTR?.;
+ TIMING(mc, cha).tsrWrTRd = 11 + RO(Proc)->Uncore.MC[mc].SLM.DTR3.tWRSR;
+/*TODO( Write to Write. Same Rank )
+ TIMING(mc, cha).tsrWrTWr = RO(Proc)->Uncore.MC[mc].SLM.DTR?.;
*/
/* Different Rank */
- TIMING(mc, cha).tdrRdTRd = \
- RO(Proc)->Uncore.MC[mc].SLM.DTR2.tRRDR;
+ TIMING(mc, cha).tdrRdTRd = RO(Proc)->Uncore.MC[mc].SLM.DTR2.tRRDR;
if (TIMING(mc, cha).tdrRdTRd > 0) {
TIMING(mc, cha).tdrRdTRd += 5;
}
- TIMING(mc, cha).tdrRdTWr = \
- + RO(Proc)->Uncore.MC[mc].SLM.DTR2.tRWDR;
+ TIMING(mc, cha).tdrRdTWr = RO(Proc)->Uncore.MC[mc].SLM.DTR2.tRWDR;
if (TIMING(mc, cha).tdrRdTWr > 0) {
TIMING(mc, cha).tdrRdTWr += 5;
}
- TIMING(mc, cha).tdrWrTRd = \
- + RO(Proc)->Uncore.MC[mc].SLM.DTR3.tWRDR;
+ TIMING(mc, cha).tdrWrTRd = RO(Proc)->Uncore.MC[mc].SLM.DTR3.tWRDR;
if (TIMING(mc, cha).tdrWrTRd > 0) {
TIMING(mc, cha).tdrWrTRd += 3;
}
- TIMING(mc, cha).tdrWrTWr = 4
- + RO(Proc)->Uncore.MC[mc].SLM.DTR2.tWWDR;
+ TIMING(mc, cha).tdrWrTWr = 4 + RO(Proc)->Uncore.MC[mc].SLM.DTR2.tWWDR;
/* Different DIMM */
- TIMING(mc, cha).tddRdTRd = \
- + RO(Proc)->Uncore.MC[mc].SLM.DTR2.tRRDD;
+ TIMING(mc, cha).tddRdTRd = RO(Proc)->Uncore.MC[mc].SLM.DTR2.tRRDD;
if (TIMING(mc, cha).tddRdTRd > 0) {
TIMING(mc, cha).tddRdTRd += 5;
}
- TIMING(mc, cha).tddRdTWr = \
- + RO(Proc)->Uncore.MC[mc].SLM.DTR2.tRWDD;
+ TIMING(mc, cha).tddRdTWr = RO(Proc)->Uncore.MC[mc].SLM.DTR2.tRWDD;
if (TIMING(mc, cha).tddRdTWr > 0) {
TIMING(mc, cha).tddRdTWr += 5;
}
- TIMING(mc, cha).tddWrTRd = 4
- + RO(Proc)->Uncore.MC[mc].SLM.DTR3.tWRDD;
+ TIMING(mc, cha).tddWrTRd = 4 + RO(Proc)->Uncore.MC[mc].SLM.DTR3.tWRDD;
- TIMING(mc, cha).tddWrTWr = 4
- + RO(Proc)->Uncore.MC[mc].SLM.DTR2.tWWDD;
+ TIMING(mc, cha).tddWrTWr = 4 + RO(Proc)->Uncore.MC[mc].SLM.DTR2.tWWDD;
/* Command Rate */
- TIMING(mc, cha).CMD_Rate = 1
- + RO(Proc)->Uncore.MC[mc].SLM.DTR1.tCMD;
+ TIMING(mc, cha).CMD_Rate = 1 + RO(Proc)->Uncore.MC[mc].SLM.DTR1.tCMD;
TIMING(mc, cha).tXS = RO(Proc)->Uncore.MC[mc].SLM.DTR0.tXS;
@@ -3190,7 +3166,212 @@
} else {
RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks = \
RO(Proc)->Uncore.MC[mc].SLM.DRP.RKEN2
- + RO(Proc)->Uncore.MC[mc].SLM.DRP.RKNE3;
+ + RO(Proc)->Uncore.MC[mc].SLM.DRP.RKEN3;
+
+ RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks = \
+ DDR3L[RO(Proc)->Uncore.MC[mc].SLM.DRP.DIMMDDEN1].Banks;
+
+ RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows = \
+ DDR3L[RO(Proc)->Uncore.MC[mc].SLM.DRP.DIMMDDEN1].Rows;
+
+ RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Cols = \
+ DDR3L[RO(Proc)->Uncore.MC[mc].SLM.DRP.DIMMDDEN1].Cols;
+ }
+ DIMM_Size = 8LLU
+ * RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows
+ * RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Cols
+ * RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks
+ * RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks;
+
+ RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Size = \
+ (unsigned int)(DIMM_Size >> 20);
+ }
+/* Error Correcting Code */
+ TIMING(mc, cha).ECC = \
+ RO(Proc)->Uncore.MC[mc].SLM.BIOS_CFG.EFF_ECC_EN
+ | RO(Proc)->Uncore.MC[mc].SLM.BIOS_CFG.ECC_EN;
+ }
+ if (RO(Proc)->Uncore.MC[mc].SLM.DRP.DRAMTYPE) {
+ RO(Shm)->Uncore.Unit.DDR_Ver = 2;
+ RO(Shm)->Uncore.Unit.DDR_Std = RAM_STD_LPDDR;
+ } else {
+ RO(Shm)->Uncore.Unit.DDR_Ver = 3;
+
+ if (RO(Proc)->Uncore.MC[mc].SLM.DRP.ENLPDDR3) {
+ RO(Shm)->Uncore.Unit.DDR_Std = RAM_STD_LPDDR;
+ } else {
+ RO(Shm)->Uncore.Unit.DDR_Std = RAM_STD_SDRAM;
+ }
+ }
+ }
+}
+
+void AMT_MCR(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) *RO(Core))
+{
+ unsigned short mc, cha, slot;
+/* BUS & DRAM frequency */
+ RO(Shm)->Uncore.CtrlSpeed = 800LLU + (
+ ((2134LLU * RO(Proc)->Uncore.MC[0].SLM.DTR0.DFREQ) >> 3)
+ );
+ RO(Shm)->Uncore.Bus.Rate = 5000;
+
+ RO(Shm)->Uncore.Bus.Speed = (RO(Core)->Clock.Hz
+ * RO(Shm)->Uncore.Bus.Rate)
+ / RO(Shm)->Proc.Features.Factory.Clock.Hz;
+
+ RO(Shm)->Uncore.Unit.Bus_Rate = MC_MTS;
+ RO(Shm)->Uncore.Unit.BusSpeed = MC_MTS;
+ RO(Shm)->Uncore.Unit.DDR_Rate = MC_NIL;
+ RO(Shm)->Uncore.Unit.DDRSpeed = MC_MHZ;
+
+ for (mc = 0; mc < RO(Shm)->Uncore.CtrlCount; mc++)
+ {
+ RO(Shm)->Uncore.MC[mc].SlotCount = RO(Proc)->Uncore.MC[mc].SlotCount;
+ RO(Shm)->Uncore.MC[mc].ChannelCount = RO(Proc)->Uncore.MC[mc].ChannelCount;
+
+ for (cha = 0; cha < RO(Shm)->Uncore.MC[mc].ChannelCount; cha++)
+ {
+/* Standard Timings */
+ TIMING(mc, cha).tCL = RO(Proc)->Uncore.MC[mc].SLM.DTR0.Z8000.tCL + 5;
+
+ TIMING(mc, cha).tRCD = RO(Proc)->Uncore.MC[mc].SLM.DTR0.Z8000.tRCD + 5;
+
+ TIMING(mc, cha).tRP = RO(Proc)->Uncore.MC[mc].SLM.DTR0.Z8000.tRP + 5;
+
+ TIMING(mc, cha).tRAS = RO(Proc)->Uncore.MC[mc].SLM.DTR1.Z8000.tRAS + 14;
+
+ TIMING(mc, cha).tRRD = RO(Proc)->Uncore.MC[mc].SLM.DTR1.Z8000.tRRD + 4;
+
+ TIMING(mc, cha).tRFC = \
+ RO(Proc)->Uncore.MC[mc].SLM.DTR0.Z8000.tXS == 0 ? 256 : 384;
+
+ switch (RO(Proc)->Uncore.MC[mc].SLM.DRFC.Z8000.tREFI) {
+ case 0 ... 1:
+ TIMING(mc, cha).tREFI = 0;
+ break;
+ case 2:
+ TIMING(mc, cha).tREFI = 39;
+ break;
+ case 3:
+ TIMING(mc, cha).tREFI = 78;
+ break;
+ }
+ TIMING(mc, cha).tREFI *= RO(Shm)->Uncore.CtrlSpeed;
+ TIMING(mc, cha).tREFI /= 20;
+
+ TIMING(mc, cha).tCKE = RO(Proc)->Uncore.MC[mc].SLM.DRMC.Z8000.CKEVAL;
+
+ TIMING(mc, cha).tRTPr= RO(Proc)->Uncore.MC[mc].SLM.DTR1.Z8000.tRTP + 4;
+
+ TIMING(mc, cha).tWTPr= RO(Proc)->Uncore.MC[mc].SLM.DTR1.Z8000.tWTP + 15;
+
+ switch (RO(Proc)->Uncore.MC[mc].SLM.DTR1.Z8000.tCCD) {
+ case 0:
+ TIMING(mc, cha).B2B = 4;
+ break;
+ case 1:
+ TIMING(mc, cha).B2B = 12;
+ break;
+ case 2:
+ TIMING(mc, cha).B2B = 18;
+ break;
+ case 3:
+ default:
+ TIMING(mc, cha).B2B = 0;
+ break;
+ }
+
+ switch (RO(Proc)->Uncore.MC[mc].SLM.DTR1.Z8000.tFAW) {
+ case 0 ... 1:
+ case 0xd ... 0xf:
+ TIMING(mc, cha).tFAW = 0;
+ break;
+ default:
+ TIMING(mc, cha).tFAW = \
+ 10 + ((unsigned int)RO(Proc)->Uncore.MC[mc].SLM.DTR1.Z8000.tFAW << 1);
+ break;
+ }
+
+ TIMING(mc, cha).tCWL = RO(Proc)->Uncore.MC[mc].SLM.DTR1.Z8000.tWCL + 3;
+
+/*TODO( Read to Read. Same Rank )
+ TIMING(mc, cha).tsrRdTRd = RO(Proc)->Uncore.MC[mc].SLM.DTR?.;
+*/
+ TIMING(mc, cha).tsrRdTWr = 6
+ + RO(Proc)->Uncore.MC[mc].SLM.DTR3.Z8000.tRWSR;
+
+ TIMING(mc, cha).tsrWrTRd = 11
+ + RO(Proc)->Uncore.MC[mc].SLM.DTR3.Z8000.tWRSR;
+/*TODO( Write to Write. Same Rank )
+ TIMING(mc, cha).tsrWrTWr = RO(Proc)->Uncore.MC[mc].SLM.DTR?.;
+*/
+/* Different Rank */
+ TIMING(mc, cha).tdrRdTRd = RO(Proc)->Uncore.MC[mc].SLM.DTR2.Z8000.tRRDR;
+ if (TIMING(mc, cha).tdrRdTRd > 0) {
+ TIMING(mc, cha).tdrRdTRd += 5;
+ }
+
+ TIMING(mc, cha).tdrRdTWr = RO(Proc)->Uncore.MC[mc].SLM.DTR2.Z8000.tRWDR;
+ if (TIMING(mc, cha).tdrRdTWr > 0) {
+ TIMING(mc, cha).tdrRdTWr += 5;
+ }
+
+ TIMING(mc, cha).tdrWrTRd = RO(Proc)->Uncore.MC[mc].SLM.DTR3.Z8000.tWRDR;
+ if (TIMING(mc, cha).tdrWrTRd > 0) {
+ TIMING(mc, cha).tdrWrTRd += 3;
+ }
+
+ TIMING(mc, cha).tdrWrTWr = RO(Proc)->Uncore.MC[mc].SLM.DTR2.Z8000.tWWDR;
+ if (TIMING(mc, cha).tdrWrTWr > 1) {
+ TIMING(mc, cha).tdrWrTWr += 4;
+ }
+/*TODO( Different DIMM )
+ TIMING(mc, cha).tddRdTRd = RO(Proc)->Uncore.MC[mc].SLM.DTR2.Z8000.tRRDD;
+
+ TIMING(mc, cha).tddRdTWr = RO(Proc)->Uncore.MC[mc].SLM.DTR2.Z8000.tRWDD;
+
+ TIMING(mc, cha).tddWrTRd = RO(Proc)->Uncore.MC[mc].SLM.DTR3.Z8000.tWRDD;
+
+ TIMING(mc, cha).tddWrTWr = RO(Proc)->Uncore.MC[mc].SLM.DTR2.Z8000.tWWDD;
+*/
+/* Command Rate */
+ TIMING(mc, cha).CMD_Rate = 1
+ + RO(Proc)->Uncore.MC[mc].SLM.DTR1.Z8000.tCMD;
+
+ TIMING(mc, cha).tXS = RO(Proc)->Uncore.MC[mc].SLM.DTR0.Z8000.tXS;
+
+ TIMING(mc, cha).tXP = RO(Proc)->Uncore.MC[mc].SLM.DTR3.Z8000.tXP;
+/* Topology */
+ for (slot = 0; slot < RO(Shm)->Uncore.MC[mc].SlotCount; slot++)
+ {
+ unsigned long long DIMM_Size;
+ const struct {
+ unsigned int Banks,
+ Rows,
+ Cols;
+ } DDR3L[4] = {
+ { .Banks = 8, .Rows = 1<<14, .Cols = 1<<10 },
+ { .Banks = 8, .Rows = 1<<15, .Cols = 1<<10 },
+ { .Banks = 8, .Rows = 1<<16, .Cols = 1<<10 },
+ { .Banks = 8, .Rows = 1<<14, .Cols = 1<<10 }
+ };
+ if (cha == 0) {
+ RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks = \
+ RO(Proc)->Uncore.MC[mc].SLM.DRP.RKEN0
+ + RO(Proc)->Uncore.MC[mc].SLM.DRP.RKEN1;
+
+ RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks = \
+ DDR3L[RO(Proc)->Uncore.MC[mc].SLM.DRP.DIMMDDEN0].Banks;
+
+ RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows = \
+ DDR3L[RO(Proc)->Uncore.MC[mc].SLM.DRP.DIMMDDEN0].Rows;
+
+ RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Cols = \
+ DDR3L[RO(Proc)->Uncore.MC[mc].SLM.DRP.DIMMDDEN0].Cols;
+ } else {
+ RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks = \
+ RO(Proc)->Uncore.MC[mc].SLM.DRP.RKEN2
+ + RO(Proc)->Uncore.MC[mc].SLM.DRP.RKEN3;
RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks = \
DDR3L[RO(Proc)->Uncore.MC[mc].SLM.DRP.DIMMDDEN1].Banks;
@@ -4401,12 +4582,21 @@
for (cha = 0; cha < RO(Shm)->Uncore.MC[mc].ChannelCount; cha++)
{
- TIMING(mc, cha).tCL = \
+ TIMING(mc, cha).tCL = \
RO(Proc)->Uncore.MC[mc].Channel[cha].SKL.ODT.tCL;
- TIMING(mc, cha).tRCD = \
+ TIMING(mc, cha).tRCD_RD = \
RO(Proc)->Uncore.MC[mc].Channel[cha].SKL.Timing.tRP;
+ TIMING(mc, cha).tRCD_WR = \
+ RO(Proc)->Uncore.MC[mc].Channel[cha].SKL.ACT.tRCD_WR;
+
+ if (TIMING(mc, cha).tRCD_WR == 0) {
+ /* ACT to CAS (RD or WR) same bank minimum delay in DCLK cycles */
+ TIMING(mc, cha).tRCD_WR = \
+ RO(Proc)->Uncore.MC[mc].Channel[cha].SKL.Timing.tRP;
+ }
+
TIMING(mc, cha).tRP = \
RO(Proc)->Uncore.MC[mc].Channel[cha].SKL.Timing.tRP;
@@ -4687,8 +4877,16 @@
TIMING(mc, cha).tCL = \
RO(Proc)->Uncore.MC[mc].Channel[cha].RKL.ODT.tCL;
- TIMING(mc, cha).tRCD = \
+ TIMING(mc, cha).tRCD_RD = \
+ RO(Proc)->Uncore.MC[mc].Channel[cha].RKL.Timing.tRP;
+
+ TIMING(mc, cha).tRCD_WR = \
+ RO(Proc)->Uncore.MC[mc].Channel[cha].RKL.ACT.tRCD_WR;
+
+ if (TIMING(mc, cha).tRCD_WR == 0) {
+ TIMING(mc, cha).tRCD_WR = \
RO(Proc)->Uncore.MC[mc].Channel[cha].RKL.Timing.tRP;
+ }
TIMING(mc, cha).tRP = \
RO(Proc)->Uncore.MC[mc].Channel[cha].RKL.Timing.tRP;
@@ -4995,8 +5193,10 @@
TIMING(mc, cha).tCL = \
RO(Proc)->Uncore.MC[mc].Channel[cha].TGL.ODT.tCL;
- TIMING(mc, cha).tRCD = \
- RO(Proc)->Uncore.MC[mc].Channel[cha].TGL.Timing.tRP;
+ /* ACT to CAS (RD or WR) same bank minimum delay in tCK */
+ TIMING(mc, cha).tRCD_RD = \
+ TIMING(mc, cha).tRCD_WR = \
+ RO(Proc)->Uncore.MC[mc].Channel[cha].TGL.Timing.tRCD;
TIMING(mc, cha).tRP = \
RO(Proc)->Uncore.MC[mc].Channel[cha].TGL.Timing.tRP;
@@ -5197,12 +5397,17 @@
TIMING(mc, cha).tCL = \
RO(Proc)->Uncore.MC[mc].Channel[cha].ADL.ODT.tCL;
- TIMING(mc, cha).tRCD = \
+ TIMING(mc, cha).tRCD_RD = \
RO(Proc)->Uncore.MC[mc].Channel[cha].ADL.Timing.tRCD;
TIMING(mc, cha).tRCD_WR = \
RO(Proc)->Uncore.MC[mc].Channel[cha].ADL.Timing.tRCDW;
+ if (TIMING(mc, cha).tRCD_WR == 0) {
+ TIMING(mc, cha).tRCD_WR = \
+ RO(Proc)->Uncore.MC[mc].Channel[cha].ADL.Timing.tRCD;
+ }
+
TIMING(mc, cha).tRP = \
RO(Proc)->Uncore.MC[mc].Channel[cha].ADL.Timing.tRP;
@@ -6338,7 +6543,7 @@
SET_CHIPSET(IC_BAYTRAIL);
break;
case DID_INTEL_AIRMONT_HB:
- SLM_PTR(RO(Shm), RO(Proc), RO(Core));
+ AMT_MCR(RO(Shm), RO(Proc), RO(Core));
SET_CHIPSET(IC_AIRMONT);
break;
case DID_INTEL_X58_HUB_CTRL:
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.95.1/corefreqk.c
new/CoreFreq-1.95.2/corefreqk.c
--- old/CoreFreq-1.95.1/corefreqk.c 2023-01-23 00:29:55.000000000 +0100
+++ new/CoreFreq-1.95.2/corefreqk.c 2023-02-05 15:34:56.000000000 +0100
@@ -5396,6 +5396,13 @@
pci_read_config_dword(dev, 0xd4,
&PUBLIC(RO(Proc))->Uncore.MC[0].SLM.DRFC.value);
+/* DRMC */
+ MsgCtrlReg.Offset = 0xb;
+
+ pci_write_config_dword(dev, 0xd0, MsgCtrlReg.value);
+
+ pci_read_config_dword(dev, 0xd4,
+ &PUBLIC(RO(Proc))->Uncore.MC[0].SLM.DRMC.value);
/* BIOS_CFG */
MsgCtrlReg.Port = 0x4;
MsgCtrlReg.Offset = 0x6;
@@ -5416,7 +5423,7 @@
| PUBLIC(RO(Proc))->Uncore.MC[0].SLM.DRP.RKEN1
) + (
PUBLIC(RO(Proc))->Uncore.MC[0].SLM.DRP.RKEN2
- | PUBLIC(RO(Proc))->Uncore.MC[0].SLM.DRP.RKNE3
+ | PUBLIC(RO(Proc))->Uncore.MC[0].SLM.DRP.RKEN3
);
return (PCI_CALLBACK) 0;
}
@@ -8191,7 +8198,7 @@
PRIVATE(OF(Zen)).Device.DF );
/* Junction Temperature */
Pkg->PowerThermal.Param.Offset[THERMAL_TARGET] = \
- PUBLIC(RO(Proc))->PowerThermal.Zen.PWR.TjMax;
+ Pkg->PowerThermal.Zen.PWR.TjMax;
/* Thermal Design Power */
Core_AMD_SMN_Read( Pkg->PowerThermal.Zen.TDP,
SMU_AMD_F17H_ZEN2_MCM_TDP,
@@ -10255,6 +10262,7 @@
{_Tremont_Elkhartlake, 1, 1, 1, 0},
{_Tremont_Jasperlake, 1, 1, 1, 0},
{_Sapphire_Rapids, 1, 1, 1, 0},
+ {_Emerald_Rapids, 1, 1, 1, 0},
{_Rocketlake, 1, 1, 1, 0},
{_Rocketlake_U , 1, 1, 1, 0},
{_Alderlake_S, 1, 1, 0, 0}, /* 06_97 */
@@ -13034,9 +13042,10 @@
BITSET_CC(LOCKLESS, PUBLIC(RO(Proc))->SPEC_CTRL_Mask, Core->Bind);
BITSET_CC(LOCKLESS, PUBLIC(RO(Proc))->ARCH_CAP_Mask , Core->Bind);
-
+ /* Per SMT, initialize with the saved thermal parameters */
+ if (Core->PowerThermal.Sensor == 0) {
Core->PowerThermal.Param = PUBLIC(RO(Proc))->PowerThermal.Param;
-
+ }
/* Collaborative Processor Performance Control */
if (PUBLIC(RO(Proc))->Features.HWP_Enable)
{
@@ -23043,7 +23052,7 @@
CoreFreqK_Register_NMI();
}
- pr_info(KERN_INFO "CoreFreq(%u:%d:%d):" \
+ pr_info("CoreFreq(%u:%d:%d):" \
" Processor [%2X%1X_%1X%1X]" \
" Architecture [%s] %3s [%u/%u]\n",
PUBLIC(RO(Proc))->Service.Core,
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.95.1/corefreqk.h
new/CoreFreq-1.95.2/corefreqk.h
--- old/CoreFreq-1.95.1/corefreqk.h 2023-01-23 00:29:55.000000000 +0100
+++ new/CoreFreq-1.95.2/corefreqk.h 2023-02-05 15:34:56.000000000 +0100
@@ -1753,6 +1753,7 @@
/* [Tremont/Jacobsville] 06_86h [Snow Ridge]
[Tremont/Lakefield] 06_8Ah
[Sapphire Rapids] 06_8Fh SPR
+ [Emerald Rapids/X] 06_CFh 7 nm EMR
[Tremont/Elkhart Lake] 06_96h
[Tremont/Jasper Lake] 06_9Ch */
#define _Tremont_Jacobsville \
@@ -1761,6 +1762,8 @@
{.ExtFamily=0x0, .Family=0x6, .ExtModel=0x8, .Model=0xA}
#define _Sapphire_Rapids \
{.ExtFamily=0x0, .Family=0x6, .ExtModel=0x8, .Model=0xF}
+#define _Emerald_Rapids \
+ {.ExtFamily=0x0, .Family=0x6, .ExtModel=0xC, .Model=0xF}
#define _Tremont_Elkhartlake \
{.ExtFamily=0x0, .Family=0x6, .ExtModel=0x9, .Model=0x6}
#define _Tremont_Jasperlake \
@@ -1876,7 +1879,6 @@
/* [GraniteRapids/X] 06_ADh GNR
[GraniteRapids/D] 06_AEh
[SierraForest/X] 06_AFh SRF
- [EmeraldRapids/X] 06_CFh 7 nm EMR
[Grand Ridge] 06_B6h */
/* [Family 0Fh] 0F_00h */
@@ -3310,6 +3312,7 @@
static char *Arch_Tremont_Elkhartlake[] = ZLIST("Tremont/Elkhart Lake");
static char *Arch_Tremont_Jasperlake[] = ZLIST("Tremont/Jasper Lake");
static char *Arch_Sapphire_Rapids[] = ZLIST("Sapphire Rapids");
+static char *Arch_Emerald_Rapids[] = ZLIST("Emerald Rapids");
static char *Arch_Rocketlake[] = ZLIST("Rocket Lake");
static char *Arch_Rocketlake_U[] = ZLIST("Rocket Lake/U");
static char *Arch_Alderlake_S[] = ZLIST("Alder Lake");
@@ -3386,7 +3389,8 @@
};
enum {
CN_CEZANNE,
- CN_BARCELO
+ CN_BARCELO,
+ CN_BARCELO_R
};
enum {
CN_MILAN
@@ -3395,7 +3399,8 @@
CN_CHAGALL
};
enum {
- CN_REMBRANDT
+ CN_REMBRANDT,
+ CN_REMBRANDT_R
};
enum {
CN_GENOA
@@ -3456,7 +3461,8 @@
);
static char *Arch_AMD_Zen3_CZN[] = ZLIST(
[CN_CEZANNE] = "Zen3/Cezanne",
- [CN_BARCELO] = "Zen3/Barcelo"
+ [CN_BARCELO] = "Zen3/Barcelo",
+ [CN_BARCELO_R] = "Zen3/Barcelo-R"
);
static char *Arch_AMD_EPYC_Milan[] = ZLIST(
[CN_MILAN] = "EPYC/Milan"
@@ -3467,7 +3473,8 @@
static char *Arch_AMD_Zen3_Badami[] = ZLIST("Zen3/Milan-X");
static char *Arch_AMD_Zen3Plus_RMB[] = ZLIST(
- [CN_REMBRANDT] = "Zen3+ Rembrandt"
+ [CN_REMBRANDT] = "Zen3+ Rembrandt",
+ [CN_REMBRANDT_R] = "Zen3+ Rembrandt-R"
);
static char *Arch_AMD_Zen4_Genoa[] = ZLIST(
[CN_GENOA] = "EPYC/Genoa"
@@ -6328,11 +6335,7 @@
},
{
.Brand = ZLIST( "AMD Ryzen 7 5825U", \
- "AMD Ryzen 7 PRO 5875U",\
- "AMD Ryzen 7 7730U", \
- "AMD Ryzen 7 PRO 7730U",\
- "AMD Ryzen 5 7530U", \
- "AMD Ryzen 5 PRO 7530U" ),
+ "AMD Ryzen 7 PRO 5875U" ),
.Boost = {+25, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_BARCELO,
@@ -6376,11 +6379,25 @@
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
+ .Brand = ZLIST( "AMD Ryzen 7 7730U", \
+ "AMD Ryzen 7 PRO 7730U",\
+ "AMD Ryzen 5 7530U", \
+ "AMD Ryzen 5 PRO 7530U" ),
+ .Boost = {+25, 0},
+ .Param.Offset = {0, 0, 0},
+ .CodeNameIdx = CN_BARCELO_R,
+ .TgtRatioUnlocked = 1,
+ .ClkRatioUnlocked = 0b10,
+ .TurboUnlocked = 0,
+ .UncoreUnlocked = 0,
+ .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
+ },
+ {
.Brand = ZLIST( "AMD Ryzen 3 7330U", \
"AMD Ryzen 3 PRO 7330U" ),
.Boost = {+20, 0},
.Param.Offset = {0, 0, 0},
- .CodeNameIdx = CN_BARCELO,
+ .CodeNameIdx = CN_BARCELO_R,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
@@ -6643,10 +6660,11 @@
},
{
.Brand = ZLIST( "AMD Ryzen 3 7335U", \
- "AMD Ryzen 5 7535HS" ),
+ "AMD Ryzen 5 7535HS", \
+ "AMD Ryzen 5 7535H" ),
.Boost = {+13, 0},
.Param.Offset = {0, 0, 0},
- .CodeNameIdx = CN_REMBRANDT,
+ .CodeNameIdx = CN_REMBRANDT_R,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
@@ -6658,7 +6676,7 @@
.Brand = ZLIST("AMD Ryzen 5 7535U"),
.Boost = {+17, 0},
.Param.Offset = {0, 0, 0},
- .CodeNameIdx = CN_REMBRANDT,
+ .CodeNameIdx = CN_REMBRANDT_R,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
@@ -6667,10 +6685,11 @@
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
- .Brand = ZLIST("AMD Ryzen 7 7735HS"),
+ .Brand = ZLIST( "AMD Ryzen 7 7735HS", \
+ "AMD Ryzen 7 7735H" ),
.Boost = {+16, 0},
.Param.Offset = {0, 0, 0},
- .CodeNameIdx = CN_REMBRANDT,
+ .CodeNameIdx = CN_REMBRANDT_R,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
@@ -6682,7 +6701,19 @@
.Brand = ZLIST("AMD Ryzen 7 7735U"),
.Boost = {+21, 0},
.Param.Offset = {0, 0, 0},
- .CodeNameIdx = CN_REMBRANDT,
+ .CodeNameIdx = CN_REMBRANDT_R,
+ .TgtRatioUnlocked = 1,
+ .ClkRatioUnlocked = 0b10,
+ .TurboUnlocked = 0,
+ .UncoreUnlocked = 0,
+ .HSMP_Capable = 0,
+ .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
+ },
+ {
+ .Brand = ZLIST("AMD Ryzen 7 7736U"),
+ .Boost = {+20, 0},
+ .Param.Offset = {0, 0, 0},
+ .CodeNameIdx = CN_REMBRANDT_R,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 0,
@@ -9412,8 +9443,32 @@
.SystemDriver = Intel_Driver,
.Architecture = Arch_Sapphire_Rapids
},
+[Emerald_Rapids] = { /* 72*/
+ .Signature = _Emerald_Rapids,
+ .Query = Query_Skylake,
+ .Update = PerCore_Skylake_Query,
+ .Start = Start_Skylake,
+ .Stop = Stop_Skylake,
+ .Exit = NULL,
+ .Timer = InitTimer_Skylake,
+ .BaseClock = BaseClock_Skylake,
+ .ClockMod = ClockMod_Skylake_HWP,
+ .TurboClock = Intel_Turbo_Config8C,
+ .thermalFormula = THERMAL_FORMULA_INTEL,
+ .voltageFormula = VOLTAGE_FORMULA_INTEL_SNB,
+ .powerFormula = POWER_FORMULA_INTEL,
+ .PCI_ids = PCI_Void_ids,
+ .Uncore = {
+ .Start = Start_Uncore_Skylake,
+ .Stop = Stop_Uncore_Skylake,
+ .ClockMod = Haswell_Uncore_Ratio
+ },
+ .Specific = Void_Specific,
+ .SystemDriver = Intel_Driver,
+ .Architecture = Arch_Emerald_Rapids
+ },
-[Rocketlake] = { /* 72*/
+[Rocketlake] = { /* 73*/
.Signature = _Rocketlake,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
@@ -9437,7 +9492,7 @@
.SystemDriver = SKL_Driver,
.Architecture = Arch_Rocketlake
},
-[Rocketlake_U] = { /* 73*/
+[Rocketlake_U] = { /* 74*/
.Signature = _Rocketlake_U,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
@@ -9462,7 +9517,7 @@
.Architecture = Arch_Rocketlake_U
},
-[Alderlake_S] = { /* 74*/
+[Alderlake_S] = { /* 75*/
.Signature = _Alderlake_S,
.Query = Query_Skylake,
.Update = PerCore_Kaby_Lake_Query,
@@ -9486,7 +9541,7 @@
.SystemDriver = SKL_Driver,
.Architecture = Arch_Alderlake_S
},
-[Alderlake_H] = { /* 75*/
+[Alderlake_H] = { /* 76*/
.Signature = _Alderlake_H,
.Query = Query_Skylake,
.Update = PerCore_Kaby_Lake_Query,
@@ -9510,7 +9565,7 @@
.SystemDriver = SKL_Driver,
.Architecture = Arch_Alderlake_H
},
-[Alderlake_N] = { /* 76*/
+[Alderlake_N] = { /* 77*/
.Signature = _Alderlake_N,
.Query = Query_Skylake,
.Update = PerCore_Kaby_Lake_Query,
@@ -9535,7 +9590,7 @@
.Architecture = Arch_Alderlake_N
},
-[Meteorlake_M] = { /* 77*/
+[Meteorlake_M] = { /* 78*/
.Signature = _Meteorlake_M,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
@@ -9559,7 +9614,7 @@
.SystemDriver = SKL_Driver,
.Architecture = Arch_Meteorlake_M
},
-[Meteorlake_N] = { /* 78*/
+[Meteorlake_N] = { /* 79*/
.Signature = _Meteorlake_N,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
@@ -9583,7 +9638,7 @@
.SystemDriver = SKL_Driver,
.Architecture = Arch_Meteorlake_N
},
-[Meteorlake_S] = { /* 79*/
+[Meteorlake_S] = { /* 80*/
.Signature = _Meteorlake_S,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
@@ -9607,7 +9662,7 @@
.SystemDriver = SKL_Driver,
.Architecture = Arch_Meteorlake_S
},
-[Raptorlake] = { /* 80*/
+[Raptorlake] = { /* 81*/
.Signature = _Raptorlake,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
@@ -9623,15 +9678,15 @@
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_ADL_RPL_ids,
.Uncore = {
- .Start = NULL,
- .Stop = NULL,
+ .Start = Start_Uncore_Alderlake,
+ .Stop = Stop_Uncore_Alderlake,
.ClockMod = Haswell_Uncore_Ratio
},
.Specific = Void_Specific,
.SystemDriver = SKL_Driver,
.Architecture = Arch_Raptorlake
},
-[Raptorlake_P] = { /* 81*/
+[Raptorlake_P] = { /* 82*/
.Signature = _Raptorlake_P,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
@@ -9647,15 +9702,15 @@
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_ADL_RPL_ids,
.Uncore = {
- .Start = NULL,
- .Stop = NULL,
+ .Start = Start_Uncore_Alderlake,
+ .Stop = Stop_Uncore_Alderlake,
.ClockMod = Haswell_Uncore_Ratio
},
.Specific = Void_Specific,
.SystemDriver = SKL_Driver,
.Architecture = Arch_Raptorlake_P
},
-[Raptorlake_S] = { /* 82*/
+[Raptorlake_S] = { /* 83*/
.Signature = _Raptorlake_S,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
@@ -9671,8 +9726,8 @@
.powerFormula = POWER_FORMULA_INTEL,
.PCI_ids = PCI_ADL_RPL_ids,
.Uncore = {
- .Start = NULL,
- .Stop = NULL,
+ .Start = Start_Uncore_Alderlake,
+ .Stop = Stop_Uncore_Alderlake,
.ClockMod = Haswell_Uncore_Ratio
},
.Specific = Void_Specific,
@@ -9680,7 +9735,7 @@
.Architecture = Arch_Raptorlake_S
},
-[AMD_Zen] = { /* 83*/
+[AMD_Zen] = { /* 84*/
.Signature = _AMD_Zen,
.Query = Query_AMD_F17h_PerSocket,
.Update = PerCore_AMD_Family_17h_Query,
@@ -9704,7 +9759,7 @@
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen
},
-[AMD_Zen_APU] = { /* 84*/
+[AMD_Zen_APU] = { /* 85*/
.Signature = _AMD_Zen_APU,
.Query = Query_AMD_F17h_PerSocket,
.Update = PerCore_AMD_Family_17h_Query,
@@ -9728,7 +9783,7 @@
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen_APU
},
-[AMD_ZenPlus] = { /* 85*/
+[AMD_ZenPlus] = { /* 86*/
.Signature = _AMD_ZenPlus,
.Query = Query_AMD_F17h_PerSocket,
.Update = PerCore_AMD_Family_17h_Query,
@@ -9752,7 +9807,7 @@
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_ZenPlus
},
-[AMD_ZenPlus_APU] = { /* 86*/
+[AMD_ZenPlus_APU] = { /* 87*/
.Signature = _AMD_ZenPlus_APU,
.Query = Query_AMD_F17h_PerSocket,
.Update = PerCore_AMD_Family_17h_Query,
@@ -9776,7 +9831,7 @@
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_ZenPlus_APU
},
-[AMD_Zen_Dali] = { /* 87*/
+[AMD_Zen_Dali] = { /* 88*/
.Signature = _AMD_Zen_Dali,
.Query = Query_AMD_F17h_PerSocket,
.Update = PerCore_AMD_Family_17h_Query,
@@ -9800,7 +9855,7 @@
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen_Dali
},
-[AMD_EPYC_Rome_CPK] = { /* 88*/
+[AMD_EPYC_Rome_CPK] = { /* 89*/
.Signature = _AMD_EPYC_Rome_CPK,
.Query = Query_AMD_F17h_PerCluster,
.Update = PerCore_AMD_Family_17h_Query,
@@ -9824,7 +9879,7 @@
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_EPYC_Rome_CPK
},
-[AMD_Zen2_Renoir] = { /* 89*/
+[AMD_Zen2_Renoir] = { /* 90*/
.Signature = _AMD_Zen2_Renoir,
.Query = Query_AMD_F17h_PerSocket,
.Update = PerCore_AMD_Family_17h_Query,
@@ -9848,7 +9903,7 @@
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen2_Renoir
},
-[AMD_Zen2_LCN] = { /* 90*/
+[AMD_Zen2_LCN] = { /* 91*/
.Signature = _AMD_Zen2_LCN,
.Query = Query_AMD_F17h_PerSocket,
.Update = PerCore_AMD_Family_17h_Query,
@@ -9872,7 +9927,7 @@
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen2_LCN
},
-[AMD_Zen2_MTS] = { /* 91*/
+[AMD_Zen2_MTS] = { /* 92*/
.Signature = _AMD_Zen2_MTS,
.Query = Query_AMD_F17h_PerCluster,
.Update = PerCore_AMD_Family_17h_Query,
@@ -9896,7 +9951,7 @@
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen2_MTS
},
-[AMD_Zen2_Ariel] = { /* 92*/
+[AMD_Zen2_Ariel] = { /* 93*/
.Signature = _AMD_Zen2_Ariel,
.Query = Query_AMD_F17h_PerCluster,
.Update = PerCore_AMD_Family_17h_Query,
@@ -9920,7 +9975,7 @@
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen2_Ariel
},
-[AMD_Zen2_Jupiter] = { /* 93*/
+[AMD_Zen2_Jupiter] = { /* 94*/
.Signature = _AMD_Zen2_Jupiter,
.Query = Query_AMD_F17h_PerCluster,
.Update = PerCore_AMD_Family_17h_Query,
@@ -9944,7 +9999,7 @@
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen2_Jupiter
},
-[AMD_Zen2_MDN] = { /* 94*/
+[AMD_Zen2_MDN] = { /* 95*/
.Signature = _AMD_Zen2_MDN,
.Query = Query_AMD_F17h_PerCluster,
.Update = PerCore_AMD_Family_17h_Query,
@@ -9968,7 +10023,7 @@
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen2_MDN
},
-[AMD_Zen3_VMR] = { /* 95*/
+[AMD_Zen3_VMR] = { /* 96*/
.Signature = _AMD_Zen3_VMR,
.Query = Query_AMD_F19h_PerCluster,
.Update = PerCore_AMD_Family_19h_Query,
@@ -9992,7 +10047,7 @@
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen3_VMR
},
-[AMD_Zen3_CZN] = { /* 96*/
+[AMD_Zen3_CZN] = { /* 97*/
.Signature = _AMD_Zen3_CZN,
.Query = Query_AMD_F19h_PerSocket,
.Update = PerCore_AMD_Family_19h_Query,
@@ -10016,7 +10071,7 @@
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen3_CZN
},
-[AMD_EPYC_Milan] = { /* 97*/
+[AMD_EPYC_Milan] = { /* 98*/
.Signature = _AMD_EPYC_Milan,
.Query = Query_AMD_F19h_PerCluster,
.Update = PerCore_AMD_Family_19h_Query,
@@ -10040,7 +10095,7 @@
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_EPYC_Milan
},
-[AMD_Zen3_Chagall] = { /* 98*/
+[AMD_Zen3_Chagall] = { /* 99*/
.Signature = _AMD_Zen3_Chagall,
.Query = Query_AMD_F19h_PerCluster,
.Update = PerCore_AMD_Family_19h_Query,
@@ -10064,7 +10119,7 @@
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen3_Chagall
},
-[AMD_Zen3_Badami] = { /* 99*/
+[AMD_Zen3_Badami] = { /*100*/
.Signature = _AMD_Zen3_Badami,
.Query = Query_AMD_F19h_PerCluster,
.Update = PerCore_AMD_Family_19h_Query,
@@ -10088,7 +10143,7 @@
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen3_Badami
},
-[AMD_Zen3Plus_RMB] = { /*100*/
+[AMD_Zen3Plus_RMB] = { /*101*/
.Signature = _AMD_Zen3Plus_RMB,
.Query = Query_AMD_F19h_PerSocket,
.Update = PerCore_AMD_Family_19h_Query,
@@ -10112,7 +10167,7 @@
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen3Plus_RMB
},
-[AMD_Zen4_Genoa] = { /*101*/
+[AMD_Zen4_Genoa] = { /*102*/
.Signature = _AMD_Zen4_Genoa,
.Query = Query_AMD_F19h_PerCluster,
.Update = PerCore_AMD_Family_19h_Query,
@@ -10136,7 +10191,7 @@
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen4_Genoa
},
-[AMD_Zen4_RPL] = { /*102*/
+[AMD_Zen4_RPL] = { /*103*/
.Signature = _AMD_Zen4_RPL,
.Query = Query_AMD_F19h_61h_PerCluster,
.Update = PerCore_AMD_Family_19h_Query,
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.95.1/coretypes.h
new/CoreFreq-1.95.2/coretypes.h
--- old/CoreFreq-1.95.1/coretypes.h 2023-01-23 00:29:55.000000000 +0100
+++ new/CoreFreq-1.95.2/coretypes.h 2023-02-05 15:34:56.000000000 +0100
@@ -6,7 +6,7 @@
#define COREFREQ_MAJOR 1
#define COREFREQ_MINOR 95
-#define COREFREQ_REV 1
+#define COREFREQ_REV 2
#if !defined(CORE_COUNT)
#define CORE_COUNT 256
@@ -99,6 +99,7 @@
Tremont_Elkhartlake,
Tremont_Jasperlake,
Sapphire_Rapids,
+ Emerald_Rapids,
Rocketlake,
Rocketlake_U,
Alderlake_S,
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.95.1/intel_reg.h
new/CoreFreq-1.95.2/intel_reg.h
--- old/CoreFreq-1.95.1/intel_reg.h 2023-01-23 00:29:55.000000000 +0100
+++ new/CoreFreq-1.95.2/intel_reg.h 2023-02-05 15:34:56.000000000 +0100
@@ -341,10 +341,19 @@
#define MSR_IA32_HWP_REQUEST MSR_HWP_REQUEST
#endif
+/* MSR registers related to Hardware Duty Cycling (HDC) */
#ifndef MSR_IA32_PKG_HDC_CTL
#define MSR_IA32_PKG_HDC_CTL 0x00000db0
#endif
+#ifndef MSR_IA32_PM_CTL1
+ #define MSR_IA32_PM_CTL1 0x00000db1
+#endif
+
+#ifndef MSR_IA32_THREAD_STALL
+ #define MSR_IA32_THREAD_STALL 0x00000db2
+#endif
+
/* Source: Intel Atom Processor E3800 Product Family Datasheet */
#define MSR_PKG_TURBO_CFG 0x00000670
#define MSR_THERM_CFG1 0x00000673
@@ -390,6 +399,20 @@
#define MSR_PKGC7_IRTL 0x0000060c
#endif
+/* Additional MSRs supported by 6th up to 13th Gen and Xeon scalable */
+#ifndef MSR_PPERF
+ #define MSR_PPERF 0x0000064e
+#endif
+
+#ifndef MSR_ANY_CORE_C0
+ #ifdef MSR_PKG_ANY_CORE_C0_RES
+ #define MSR_ANY_CORE_C0 MSR_PKG_ANY_CORE_C0_RES
+ #else
+ #define MSR_ANY_CORE_C0 0x00000659
+ #endif
+#endif
+
+/* Partially documented registers */
#define MSR_FLEX_RATIO 0x00000194
#define MSR_IA32_OVERCLOCKING_STATUS 0x00000195
#define MSR_IA32_MISC_PACKAGE_CTLS 0x000000bc
@@ -2474,7 +2497,7 @@
RKEN0 : 1-0, /* DIMM 0, Rank 0 Enabled */
RKEN1 : 2-1, /* DIMM 0, Rank 1 Enabled */
RKEN2 : 3-2, /* DIMM 1, Rank 0 Enabled */
- RKNE3 : 4-3, /* DIMM 1, Rank 1 Enabled */
+ RKEN3 : 4-3, /* DIMM 1, Rank 1 Enabled */
DIMMDWID0 : 6-4, /* 0b00:x8 0b01:x16 0b10:x32 0b11:RSV*/
DIMMDDEN0 : 8-6, /* Density {1; 2; 4; 8} Gbit */
ReservedBits1 : 9-8,
@@ -2652,9 +2675,24 @@
} Z8000;
} SOC_MC_DTR3;
-typedef union /* MCR: Port=0x01 */
+typedef union /* MCR: Port=0x01 & Offset=0x5 */
{
unsigned int value;
+ struct {
+ unsigned int
+ WRODTSTRT : 2-0,
+ Rsvd_32 : 4-2,
+ WRODTSTOP : 7-4,
+ Rsvd_7 : 8-7,
+ RDODTSTRT : 11-8,
+ Rsvd_24 : 12-11,
+ RDODTSTOP : 15-12,
+ Rsvd_15 : 16-15,
+ TRGSTRDIS : 17-16,
+ RDODTDIS : 18-17,
+ WRBODTDIS : 19-18,
+ Rsvd_31 : 32-19;
+ };
struct { /* Offset=0x5(DTR4A) ; 0x15(DTR4B) */
unsigned int
WRODTSTRT : 2-0, /* WR command to ODT assert delay */
@@ -2679,6 +2717,26 @@
struct {
unsigned int
SREDLY : 8-0, /* Self-Refresh Entry delay */
+ PMOP : 13-8, /* SPID Power Mode Opcode */
+ Rsvd_15 : 16-13,
+ PCLSTO : 19-16, /* 2:30;3:60;4:120;5:240;6:480;7:1000*/
+ Rsvd_19 : 20-19,
+ PCLSWKOK : 21-20, /* Wake Allowed for Page Close */
+ PREAPWDEN : 22-21, /* Precharge All Command */
+ Rsvd_22 : 23-22,
+ DYNSREN : 24-23, /* Dynamic Self-Refresh Enable */
+ CLKGTDIS : 25-24, /* Clock Gating Disabled */
+ DISPWRDN : 26-25, /* Disable Power Down */
+ BLMODE : 27-26, /* Burst Length Mode */
+ Rsvd_27 : 28-27,
+ REUTCLKGTDIS : 29-28, /* REUT Clock Gate Disable */
+ ENPHYCLKGATE : 30-29, /* Enable PHY Clock Gate During SR */
+ ENCKTRI : 31-30, /* CK/CKB TriState During PowerDown */
+ ENCORECLKGATE : 32-31; /* Enable Core Clock Gate During SR */
+ };
+ struct {
+ unsigned int
+ SREDLY : 8-0, /* Self-Refresh Entry delay */
DYNSREN : 9-8, /* Dynamic Self-Refresh Enable */
Rsvd_28 : 11-9,
DYNPMOP : 16-11,
@@ -2695,6 +2753,13 @@
unsigned int value;
struct {
unsigned int
+ CSTRIST : 1-0, /* Tristate Chip-Select. 0:Never */
+ Rsvd_3 : 4-1,
+ CMDTRIST : 6-4, /* Tristate Command if tCMD = 0 */
+ Rsvd_31 : 32-6;
+ };
+ struct {
+ unsigned int
DISPWRDN : 1-0, /* Disable Power Down */
DPMC1_Rsvd : 2-1,
PCLSWKOK : 3-2, /*Wake Allowed for Page Close Timeout*/
@@ -2743,6 +2808,36 @@
} Z8000;
} SOC_MC_DRFC;
+typedef union /* MCR: Port=0x01 & Offset=0xB */
+{
+ unsigned int value;
+ struct {
+ unsigned int
+ CKEVAL : 4-0,
+ CKEMODE : 5-4, /* CKE Control Mode */
+ Rsvd_5 : 8-5,
+ ODTVAL : 12-8,
+ ODTMODE : 13-12, /* ODT Control Mode */
+ Rsvd_13 : 16-13,
+ COLDWAKE : 17-16, /* S3 WAKE command */
+ Rsvd_17 : 32-17;
+ };
+ struct {
+ unsigned int
+ CKEVAL : 2-0,
+ Rsvd_2 : 4-2,
+ CKEMODE : 5-4,
+ Rsvd_5 : 8-5,
+ ODTVAL : 10-8,
+ Rsvd_10 : 12-10,
+ ODTMODE : 13-12,
+ Rsvd_13 : 16-13,
+ COLDWAKE : 17-16,
+ DBPTRCLR : 18-17,
+ Rsvd_18 : 32-18;
+ } Z8000;
+} SOC_MC_DRMC;
+
typedef union /* MCR: Port=0x04 & Offset=0x6 */
{
unsigned int value;
