Script 'mail_helper' called by obssrc Hello community, here is the log from the commit of package CoreFreq for openSUSE:Factory checked in at 2023-06-16 16:54:14 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/CoreFreq (Old) and /work/SRC/openSUSE:Factory/.CoreFreq.new.15902 (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "CoreFreq" Fri Jun 16 16:54:14 2023 rev:28 rq:1093269 version:1.96.4 Changes: -------- --- /work/SRC/openSUSE:Factory/CoreFreq/CoreFreq.changes 2023-06-04 16:42:57.886259076 +0200 +++ /work/SRC/openSUSE:Factory/.CoreFreq.new.15902/CoreFreq.changes 2023-06-16 16:55:26.513919001 +0200 @@ -1,0 +2,22 @@ +Thu Jun 15 11:00:33 UTC 2023 - Michael Pujos <pujos.mich...@gmail.com> + +- update to 1.96.4 + * [AMD] + - Display CPUID state of new and legacy features: + Fused Multiply Add [FMA4] + Extended Operation Support [XOP] + Translation Cache Extension [TCE] + Trailing Bit Manipulation [TBM] + OS Visible Work-around [OSVW] + LOCK prefix to read CR8 [AltMov] + * [Intel] + - Advanced Matrix Extensions [AMX] + - Bits and Features of Sierra Forest and Grand Ridge + - Attempt to decode the Meteor Lake Memory Controller + +- update to 1.96.3 + * [AMD] + - [Zeppelin] Probe more than one UMC controllers on Ryzen Threadripper 1900X + - [Zen4] Dump SMBE and BMEC sub-leaves of CPUID 0x80000020 + +------------------------------------------------------------------- Old: ---- CoreFreq-1.96.2.tar.gz New: ---- CoreFreq-1.96.4.tar.gz ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ CoreFreq.spec ++++++ --- /var/tmp/diff_new_pack.i3f8JJ/_old 2023-06-16 16:55:27.013921951 +0200 +++ /var/tmp/diff_new_pack.i3f8JJ/_new 2023-06-16 16:55:27.017921974 +0200 @@ -17,7 +17,7 @@ Name: CoreFreq -Version: 1.96.2 +Version: 1.96.4 Release: 0 Summary: CPU monitoring software for 64-bit processors License: GPL-2.0-or-later ++++++ CoreFreq-1.96.2.tar.gz -> CoreFreq-1.96.4.tar.gz ++++++ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-1.96.2/Makefile new/CoreFreq-1.96.4/Makefile --- old/CoreFreq-1.96.2/Makefile 2023-05-31 03:08:53.000000000 +0200 +++ new/CoreFreq-1.96.4/Makefile 2023-06-11 12:01:08.000000000 +0200 @@ -58,7 +58,7 @@ ccflags-y += -D MSR_CORE_PERF_URC=$(MSR_CORE_PERF_URC) ifneq ($(HWM_CHIPSET),) - ccflags-y += -D HWM_CHIPSET=$(HWM_CHIPSET) +ccflags-y += -D HWM_CHIPSET=$(HWM_CHIPSET) endif ifneq ($(NO_HEADER),) diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-1.96.2/README.md new/CoreFreq-1.96.4/README.md --- old/CoreFreq-1.96.2/README.md 2023-05-31 03:08:53.000000000 +0200 +++ new/CoreFreq-1.96.4/README.md 2023-06-11 12:01:08.000000000 +0200 @@ -189,7 +189,9 @@ ## ArchLinux * [](https://aur.archlinux.org/pkgbase/corefreq/) follows released tags -* [](https://aur.archlinux.org/pkgbase/corefreq-git/) follows `develop` branch + +## Gentoo Linux +* In [GURU overlay](https://wiki.gentoo.org/wiki/Project:GURU/Information_for_End_Users) CoreFreq [package](https://github.com/gentoo/guru/tree/master/sys-apps/corefreq), please contact [vitaly-zdanevich](https://github.com/vitaly-zdanevich) ## Debian, Ubuntu * Installing the DKMS package will pull the Kernel development packages diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-1.96.2/corefreq-api.h new/CoreFreq-1.96.4/corefreq-api.h --- old/CoreFreq-1.96.2/corefreq-api.h 2023-05-31 03:08:53.000000000 +0200 +++ new/CoreFreq-1.96.4/corefreq-api.h 2023-06-11 12:01:08.000000000 +0200 @@ -1085,6 +1085,7 @@ BitCC IPRED_DIS_S __attribute__ ((aligned (16))); BitCC RRSBA_DIS_U __attribute__ ((aligned (16))); BitCC RRSBA_DIS_S __attribute__ ((aligned (16))); + BitCC DDPD_U_DIS __attribute__ ((aligned (16))); BitCC BHI_DIS_S __attribute__ ((aligned (16))); BitCC /* AMD */ BTC_NOBR __attribute__ ((aligned (16))); @@ -1455,6 +1456,9 @@ #define DID_INTEL_RAPTORLAKE_B760_PCH 0x7a06 /* Source: Intel(R) Pentium(R) Silver N5000 CPU @ 1.10GHz */ #define DID_INTEL_GEMINILAKE_HB 0x31f0 +/* Source: Meteor Lake kernel preview: Intel(R) Core(TM) Ultra 7 1003H */ +#define DID_INTEL_METEORLAKE_M_6_8_2_HB 0x7d01 +#define DID_INTEL_METEORLAKE_PCH 0x7e02 /* Source: /include/linux/pci_ids.h */ #define DID_AMD_K8_NB_MEMCTL 0x1102 #define DID_AMD_K8_NB 0x1100 diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-1.96.2/corefreq-cli-json.c new/CoreFreq-1.96.4/corefreq-cli-json.c --- old/CoreFreq-1.96.2/corefreq-cli-json.c 2023-05-31 03:08:53.000000000 +0200 +++ new/CoreFreq-1.96.4/corefreq-cli-json.c 2023-06-11 12:01:08.000000000 +0200 @@ -691,6 +691,8 @@ json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.HWP_Idle); json_key(&s, "ITD_MSR"); json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.ITD_MSR); + json_key(&s, "THERM_INT_MSR"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.Power.EAX.THERM_INT_MSR); json_end_object(&s); } json_key(&s, "EBX"); @@ -868,6 +870,8 @@ json_key(&s, "EDX"); { json_start_object(&s); + json_key(&s, "SGX_KEYS"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature.EDX.SGX_KEYS); json_key(&s, "AVX512_4VNNIW"); json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature.EDX.AVX512_4VNNIW); json_key(&s, "AVX512_4FMAPS"); @@ -890,6 +894,18 @@ json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature.EDX.TSXLDTRK); json_key(&s, "PCONFIG"); json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature.EDX.PCONFIG); + json_key(&s, "Architectural_LBRs"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature.EDX.ArchitecturalLBRs); + json_key(&s, "CET_IBT"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature.EDX.CET_IBT); + json_key(&s, "AMX_BF16"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature.EDX.AMX_BF16); + json_key(&s, "AMX_TILE"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature.EDX.AMX_TILE); + json_key(&s, "AMX_INT8"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature.EDX.AMX_INT8); + json_key(&s, "AVX512_FP16"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature.EDX.AVX512_FP16); json_key(&s, "IBRS_IBPB"); json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature.EDX.IBRS_IBPB_Cap); json_key(&s, "STIBP"); @@ -921,6 +937,8 @@ json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature_Leaf1_EAX.AVX_VNNI_VEX); json_key(&s, "AVX512_BF16"); json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature_Leaf1_EAX.AVX512_BF16); + json_key(&s, "LASS"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature_Leaf1_EAX.LASS); json_key(&s, "CMPCCXADD"); json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature_Leaf1_EAX.CMPCCXADD); json_key(&s, "Fast_Zero_length_REP_MOVSB"); @@ -951,8 +969,10 @@ json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature_Leaf1_EDX.AVX_VNNI_INT8); json_key(&s, "AVX_NE_CONVERT"); json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature_Leaf1_EDX.AVX_NE_CONVERT); - json_key(&s, "PREFETCHITI"); - json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature_Leaf1_EDX.PREFETCHITI); + json_key(&s, "PREFETCHI"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature_Leaf1_EDX.PREFETCHI); + json_key(&s, "CET_SSS"); + json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.ExtFeature_Leaf1_EDX.CET_SSS); json_end_object(&s); } @@ -1784,6 +1804,8 @@ json_literal(&s, "%llu", RO(Shm)->Proc.Mechanisms.RRSBA_DIS_S); json_key(&s, "BHI_DIS_S"); json_literal(&s, "%llu", RO(Shm)->Proc.Mechanisms.BHI_DIS_S); + json_key(&s, "DDPD_U_DIS"); + json_literal(&s, "%llu", RO(Shm)->Proc.Mechanisms.DDPD_U_DIS); json_key(&s, "MCDT_NO"); json_literal(&s, "%llu", RO(Shm)->Proc.Mechanisms.MCDT_NO); json_key(&s, "BTC_NO"); diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-1.96.2/corefreq-cli-rsc-en.h new/CoreFreq-1.96.4/corefreq-cli-rsc-en.h --- old/CoreFreq-1.96.2/corefreq-cli-rsc-en.h 2023-05-31 03:08:53.000000000 +0200 +++ new/CoreFreq-1.96.4/corefreq-cli-rsc-en.h 2023-06-11 12:01:08.000000000 +0200 @@ -996,7 +996,12 @@ #define RSC_ISA_ADX_COMM_CODE_EN " Multi-Precision Add-Carry " #define RSC_ISA_AES_COMM_CODE_EN " Advanced Encryption Standard " +#define RSC_ISA_AMX_BF16_COMM_CODE_EN " Advanced Matrix Extensions BFLOAT16 " +#define RSC_ISA_AMX_TILE_COMM_CODE_EN " Advanced Matrix Extensions Tile " +#define RSC_ISA_AMX_INT8_COMM_CODE_EN " Advanced Matrix Extensions 8-bits " +#define RSC_ISA_AMX_FP16_COMM_CODE_EN " Advanced Matrix Extensions FP16 " #define RSC_ISA_AVX_COMM_CODE_EN " Advanced Vector Extensions " +#define RSC_ISA_CMPCCXADD_COMM_CODE_EN " CMPccXADD Instructions " #define RSC_ISA_BMI_COMM_CODE_EN " Bit Manipulation Instructions " #define RSC_ISA_CLWB_COMM_CODE_EN " Cache Line Write Back " #define RSC_ISA_CLFLUSH_COMM_CODE_EN " Flush Cache Line " @@ -1080,6 +1085,7 @@ #define RSC_FEATURES_APIC_CODE_EN "Advanced Programmable Interrupt Controller" #define RSC_FEATURES_AVIC_CODE_EN "Advanced Virtual Interrupt Controller" #define RSC_FEATURES_ARAT_CODE_EN "APIC Timer Invariance" +#define RSC_FEATURES_ALTMOV_CODE_EN "LOCK prefix to read CR8" #define RSC_FEATURES_CLZERO_CODE_EN "Clear Zero Instruction" #define RSC_FEATURES_CORE_MP_CODE_EN "Core Multi-Processing" #define RSC_FEATURES_CNXT_ID_CODE_EN "L1 Data Cache Context ID" @@ -1109,6 +1115,7 @@ #define RSC_FEATURES_INVLPGB_CODE_EN "Instruction INVLPGB" #define RSC_FEATURES_INVPCID_CODE_EN "Instruction INVPCID" #define RSC_FEATURES_LM_CODE_EN "Long Mode 64 bits" +#define RSC_FEATURES_LASS_CODE_EN "Linear Address Space Separation" #define RSC_FEATURES_LAM_CODE_EN "Linear Address Masking" #define RSC_FEATURES_LWP_CODE_EN "LightWeight Profiling" #define RSC_FEATURES_MBE_CODE_EN "Memory Bandwidth Enforcement" @@ -1119,6 +1126,7 @@ #define RSC_FEATURES_MTRR_CODE_EN "Memory Type Range Registers" #define RSC_FEATURES_NX_CODE_EN "No-Execute Page Protection" #define RSC_FEATURES_OSXSAVE_CODE_EN "OS-Enabled Ext. State Management" +#define RSC_FEATURES_OSVW_CODE_EN "OS Visible Work-around" #define RSC_FEATURES_PAE_CODE_EN "Physical Address Extension" #define RSC_FEATURES_PAT_CODE_EN "Page Attribute Table" #define RSC_FEATURES_PBE_CODE_EN "Pending Break Enable" @@ -1130,6 +1138,7 @@ #define RSC_FEATURES_PSE36_CODE_EN "36-bit Page Size Extension" #define RSC_FEATURES_PSN_CODE_EN "Processor Serial Number" #define RSC_FEATURES_PTWRITE_CODE_EN "Write Data to a Processor Trace Packet" +#define RSC_FEATURES_PREFETCHI_CODE_EN "PREFETCHIT0/1 Instructions" #define RSC_FEATURES_RDT_PQE_CODE_EN "Resource Director Technology/PQE" #define RSC_FEATURES_RDT_PQM_CODE_EN "Resource Director Technology/PQM" #define RSC_FEATURES_RDPRU_CODE_EN "Read Processor Register at User level" @@ -1139,6 +1148,8 @@ #define RSC_FEATURES_SMAP_CODE_EN "Supervisor-Mode Access Prevention" #define RSC_FEATURES_SMEP_CODE_EN "Supervisor-Mode Execution Prevention" #define RSC_FEATURES_ITD_CODE_EN "Thread Director" +#define RSC_FEATURES_TBM_CODE_EN "Trailing Bit Manipulation" +#define RSC_FEATURES_TCE_CODE_EN "Translation Cache Extension" #define RSC_FEATURES_TSC_CODE_EN "Time Stamp Counter" #define RSC_FEATURES_TSC_DEADLN_CODE_EN "Time Stamp Counter Deadline" #define RSC_FEATURES_TSXABORT_CODE_EN "TSX Force Abort MSR Register" @@ -1152,6 +1163,7 @@ #define RSC_FEATURES_XD_BIT_CODE_EN "Execution Disable Bit Support" #define RSC_FEATURES_XSAVE_CODE_EN "XSAVE/XSTOR States" #define RSC_FEATURES_XTPR_CODE_EN "xTPR Update Control" +#define RSC_FEATURES_XOP_CODE_EN "Extended Operation Support" #define RSC_FEAT_SECTION_MECH_CODE_EN "Mitigation mechanisms" #define RSC_FEAT_SECTION_SEC_CODE_EN "Security Features" @@ -2017,6 +2029,7 @@ #define RSC_MECH_IPRED_DIS_S_CODE_EN "Arch - IPRED disabled for CPL0/1/2" #define RSC_MECH_RRSBA_DIS_U_CODE_EN "Arch - RRSBA disabled for CPL3" #define RSC_MECH_RRSBA_DIS_S_CODE_EN "Arch - RRSBA disabled for CPL0/1/2" +#define RSC_MECH_DDPD_U_DIS_CODE_EN "Arch - Data Dependent Prefetcher CPL3" #define RSC_MECH_BHI_DIS_S_CODE_EN "Arch - BHI disabled for CPL0/1/2" #define RSC_MECH_MCDT_NO_CODE_EN "No MXCSR Configuration Dependent Timing" #define RSC_MECH_BTC_NO_CODE_EN "No Branch Type Confusion" @@ -2595,6 +2608,10 @@ #define RSC_ISA_3DNOW_CODE " 3DNow!/Ext [%c/%c]" #define RSC_ISA_ADX_CODE " ADX [%c]" #define RSC_ISA_AES_CODE " AES [%c]" +#define RSC_ISA_AMX_BF16_CODE " AMX-BF16 [%c]" +#define RSC_ISA_AMX_TILE_CODE " AMX-TILE [%c]" +#define RSC_ISA_AMX_INT8_CODE " AMX-INT8 [%c]" +#define RSC_ISA_AMX_FP16_CODE " AMX-FP16 [%c] " #define RSC_ISA_AVX_CODE " AVX/AVX2 [%c/%c] " #define RSC_ISA_AVX512_F_CODE " AVX512-F [%c]" #define RSC_ISA_AVX512_DQ_CODE " AVX512-DQ [%c]" @@ -2614,8 +2631,12 @@ #define RSC_ISA_AVX512_VP2I_CODE " AVX512-VP2I [%c] " #define RSC_ISA_AVX512_BF16_CODE " AVX512-BF16 [%c]" #define RSC_ISA_AVX_VEX_CODE " AVX-VNNI-VEX [%c]" +#define RSC_ISA_AVX_INT8_CODE " AVX-VNN-INT8 [%c]" +#define RSC_ISA_AVX_NE_CONV_CODE " AVX-NE-CONV [%c] " #define RSC_ISA_AVX_128_CODE " AVX-FP128 [%c]" #define RSC_ISA_AVX_256_CODE " AVX-FP256 [%c] " +#define RSC_ISA_AVX_IFMA_CODE " AVX-IFMA [%c]" +#define RSC_ISA_CMPCCXADD_CODE " CMPccXADD [%c]" #define RSC_ISA_BMI_CODE " BMI1/BMI2 [%c/%c]" #define RSC_ISA_CLWB_CODE " CLWB [%c]" #define RSC_ISA_CLFLUSH_CODE " CLFLUSH [%c]" diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-1.96.2/corefreq-cli-rsc-fr.h new/CoreFreq-1.96.4/corefreq-cli-rsc-fr.h --- old/CoreFreq-1.96.2/corefreq-cli-rsc-fr.h 2023-05-31 03:08:53.000000000 +0200 +++ new/CoreFreq-1.96.4/corefreq-cli-rsc-fr.h 2023-06-11 12:01:08.000000000 +0200 @@ -492,7 +492,12 @@ #define RSC_ISA_3DNOW_COMM_CODE_FR RSC_ISA_3DNOW_COMM_CODE_EN #define RSC_ISA_ADX_COMM_CODE_FR RSC_ISA_ADX_COMM_CODE_EN #define RSC_ISA_AES_COMM_CODE_FR RSC_ISA_AES_COMM_CODE_EN +#define RSC_ISA_AMX_BF16_COMM_CODE_FR RSC_ISA_AMX_BF16_COMM_CODE_EN +#define RSC_ISA_AMX_TILE_COMM_CODE_FR RSC_ISA_AMX_TILE_COMM_CODE_EN +#define RSC_ISA_AMX_INT8_COMM_CODE_FR RSC_ISA_AMX_INT8_COMM_CODE_EN +#define RSC_ISA_AMX_FP16_COMM_CODE_FR RSC_ISA_AMX_FP16_COMM_CODE_EN #define RSC_ISA_AVX_COMM_CODE_FR RSC_ISA_AVX_COMM_CODE_EN +#define RSC_ISA_CMPCCXADD_COMM_CODE_FR RSC_ISA_CMPCCXADD_COMM_CODE_EN #define RSC_ISA_BMI_COMM_CODE_FR RSC_ISA_BMI_COMM_CODE_EN #define RSC_ISA_CLWB_COMM_CODE_FR RSC_ISA_CLWB_COMM_CODE_EN #define RSC_ISA_CLFLUSH_COMM_CODE_FR RSC_ISA_CLFLUSH_COMM_CODE_EN @@ -554,6 +559,7 @@ #define RSC_FEATURES_APIC_CODE_FR "Advanced Programmable Interrupt Controller" #define RSC_FEATURES_AVIC_CODE_FR "Advanced Virtual Interrupt Controller" #define RSC_FEATURES_ARAT_CODE_FR "APIC Timer Invariance" +#define RSC_FEATURES_ALTMOV_CODE_FR "LOCK prefix to read CR8" #define RSC_FEATURES_CLZERO_CODE_FR "Clear Zero Instruction" #define RSC_FEATURES_CORE_MP_CODE_FR "Core Multi-Processing" #define RSC_FEATURES_CNXT_ID_CODE_FR "L1 Data Cache Context ID" @@ -583,6 +589,7 @@ #define RSC_FEATURES_INVLPGB_CODE_FR "Instruction INVLPGB" #define RSC_FEATURES_INVPCID_CODE_FR "Instruction INVPCID" #define RSC_FEATURES_LM_CODE_FR "Long Mode 64 bits" +#define RSC_FEATURES_LASS_CODE_FR "Linear Address Space Separation" #define RSC_FEATURES_LAM_CODE_FR "Linear Address Masking" #define RSC_FEATURES_LWP_CODE_FR "LightWeight Profiling" #define RSC_FEATURES_MBE_CODE_FR "Memory Bandwidth Enforcement" @@ -593,6 +600,7 @@ #define RSC_FEATURES_MTRR_CODE_FR "Memory Type Range Registers" #define RSC_FEATURES_NX_CODE_FR "No-Execute Page Protection" #define RSC_FEATURES_OSXSAVE_CODE_FR "OS-Enabled Ext. State Management" +#define RSC_FEATURES_OSVW_CODE_FR "OS Visible Work-around" #define RSC_FEATURES_PAE_CODE_FR "Physical Address Extension" #define RSC_FEATURES_PAT_CODE_FR "Page Attribute Table" #define RSC_FEATURES_PBE_CODE_FR "Pending Break Enable" @@ -604,6 +612,7 @@ #define RSC_FEATURES_PSE36_CODE_FR "36-bit Page Size Extension" #define RSC_FEATURES_PSN_CODE_FR "Processor Serial Number" #define RSC_FEATURES_PTWRITE_CODE_FR "Write Data to a Processor Trace Packet" +#define RSC_FEATURES_PREFETCHI_CODE_FR "Instructions PREFETCHIT0/1" #define RSC_FEATURES_RDT_PQE_CODE_FR "Resource Director Technology/PQE" #define RSC_FEATURES_RDT_PQM_CODE_FR "Resource Director Technology/PQM" #define RSC_FEATURES_RDPRU_CODE_FR "Read Processor Register at User level" @@ -613,6 +622,8 @@ #define RSC_FEATURES_SMAP_CODE_FR "Supervisor-Mode Access Prevention" #define RSC_FEATURES_SMEP_CODE_FR "Supervisor-Mode Execution Prevention" #define RSC_FEATURES_ITD_CODE_FR "Thread Director" +#define RSC_FEATURES_TBM_CODE_FR "Trailing Bit Manipulation" +#define RSC_FEATURES_TCE_CODE_FR "Translation Cache Extension" #define RSC_FEATURES_TSC_CODE_FR "Time Stamp Counter" #define RSC_FEATURES_TSC_DEADLN_CODE_FR "Time Stamp Counter Deadline" #define RSC_FEATURES_TSXABORT_CODE_FR "TSX Force Abort MSR Register" @@ -626,6 +637,7 @@ #define RSC_FEATURES_XD_BIT_CODE_FR "Execution Disable Bit Support" #define RSC_FEATURES_XSAVE_CODE_FR "XSAVE/XSTOR States" #define RSC_FEATURES_XTPR_CODE_FR "xTPR Update Control" +#define RSC_FEATURES_XOP_CODE_FR "Extended Operation Support" #define RSC_FEAT_SECTION_MECH_CODE_FR "M""\xa9""canismes d'att""\xa9""nuation" #define RSC_FEAT_SECTION_SEC_CODE_FR "Fonctions de s""\xa9""curit""\xa9" @@ -1483,6 +1495,7 @@ #define RSC_MECH_IPRED_DIS_S_CODE_FR RSC_MECH_IPRED_DIS_S_CODE_EN #define RSC_MECH_RRSBA_DIS_U_CODE_FR RSC_MECH_RRSBA_DIS_U_CODE_EN #define RSC_MECH_RRSBA_DIS_S_CODE_FR RSC_MECH_RRSBA_DIS_S_CODE_EN +#define RSC_MECH_DDPD_U_DIS_CODE_FR RSC_MECH_DDPD_U_DIS_CODE_EN #define RSC_MECH_BHI_DIS_S_CODE_FR RSC_MECH_BHI_DIS_S_CODE_EN #define RSC_MECH_MCDT_NO_CODE_FR RSC_MECH_MCDT_NO_CODE_EN #define RSC_MECH_BTC_NO_CODE_FR RSC_MECH_BTC_NO_CODE_EN diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-1.96.2/corefreq-cli-rsc.c new/CoreFreq-1.96.4/corefreq-cli-rsc.c --- old/CoreFreq-1.96.2/corefreq-cli-rsc.c 2023-05-31 03:08:53.000000000 +0200 +++ new/CoreFreq-1.96.4/corefreq-cli-rsc.c 2023-06-11 12:01:08.000000000 +0200 @@ -804,6 +804,14 @@ LDT(RSC_ISA_ADX_COMM), LDQ(RSC_ISA_AES), LDT(RSC_ISA_AES_COMM), + LDQ(RSC_ISA_AMX_BF16), + LDT(RSC_ISA_AMX_BF16_COMM), + LDQ(RSC_ISA_AMX_TILE), + LDT(RSC_ISA_AMX_TILE_COMM), + LDQ(RSC_ISA_AMX_INT8), + LDT(RSC_ISA_AMX_INT8_COMM), + LDQ(RSC_ISA_AMX_FP16), + LDT(RSC_ISA_AMX_FP16_COMM), LDQ(RSC_ISA_AVX), LDT(RSC_ISA_AVX_COMM), LDQ(RSC_ISA_AVX512_F), @@ -824,8 +832,13 @@ LDQ(RSC_ISA_AVX512_VP2I), LDQ(RSC_ISA_AVX512_BF16), LDQ(RSC_ISA_AVX_VEX), + LDQ(RSC_ISA_AVX_INT8), + LDQ(RSC_ISA_AVX_NE_CONV), LDQ(RSC_ISA_AVX_128), LDQ(RSC_ISA_AVX_256), + LDQ(RSC_ISA_AVX_IFMA), + LDQ(RSC_ISA_CMPCCXADD), + LDT(RSC_ISA_CMPCCXADD_COMM), LDQ(RSC_ISA_BMI), LDT(RSC_ISA_BMI_COMM), LDQ(RSC_ISA_CLWB), @@ -931,6 +944,7 @@ LDT(RSC_FEATURES_APIC), LDT(RSC_FEATURES_AVIC), LDT(RSC_FEATURES_ARAT), + LDT(RSC_FEATURES_ALTMOV), LDT(RSC_FEATURES_CLZERO), LDT(RSC_FEATURES_CORE_MP), LDT(RSC_FEATURES_CNXT_ID), @@ -955,6 +969,7 @@ LDT(RSC_FEATURES_INVLPGB), LDT(RSC_FEATURES_INVPCID), LDT(RSC_FEATURES_LM), + LDT(RSC_FEATURES_LASS), LDT(RSC_FEATURES_LAM), LDT(RSC_FEATURES_LWP), LDT(RSC_FEATURES_MBE), @@ -965,6 +980,7 @@ LDT(RSC_FEATURES_MTRR), LDT(RSC_FEATURES_NX), LDT(RSC_FEATURES_OSXSAVE), + LDT(RSC_FEATURES_OSVW), LDT(RSC_FEATURES_PAE), LDT(RSC_FEATURES_PAT), LDT(RSC_FEATURES_PBE), @@ -976,6 +992,7 @@ LDT(RSC_FEATURES_PSE36), LDT(RSC_FEATURES_PSN), LDT(RSC_FEATURES_PTWRITE), + LDT(RSC_FEATURES_PREFETCHI), LDT(RSC_FEATURES_RDT_PQE), LDT(RSC_FEATURES_RDT_PQM), LDT(RSC_FEATURES_RDPRU), @@ -985,6 +1002,8 @@ LDT(RSC_FEATURES_SMAP), LDT(RSC_FEATURES_SMEP), LDT(RSC_FEATURES_ITD), + LDT(RSC_FEATURES_TBM), + LDT(RSC_FEATURES_TCE), LDT(RSC_FEATURES_TSC), LDT(RSC_FEATURES_TSC_DEADLN), LDT(RSC_FEATURES_TSXABORT), @@ -998,6 +1017,7 @@ LDT(RSC_FEATURES_XD_BIT), LDT(RSC_FEATURES_XSAVE), LDT(RSC_FEATURES_XTPR), + LDT(RSC_FEATURES_XOP), LDT(RSC_FEAT_SECTION_MECH), LDT(RSC_FEAT_SECTION_SEC), LDT(RSC_TECHNOLOGIES_TITLE), @@ -1950,6 +1970,7 @@ LDT(RSC_MECH_IPRED_DIS_S), LDT(RSC_MECH_RRSBA_DIS_U), LDT(RSC_MECH_RRSBA_DIS_S), + LDT(RSC_MECH_DDPD_U_DIS), LDT(RSC_MECH_BHI_DIS_S), LDT(RSC_MECH_MCDT_NO), LDT(RSC_MECH_BTC_NO), diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-1.96.2/corefreq-cli-rsc.h new/CoreFreq-1.96.4/corefreq-cli-rsc.h --- old/CoreFreq-1.96.2/corefreq-cli-rsc.h 2023-05-31 03:08:53.000000000 +0200 +++ new/CoreFreq-1.96.4/corefreq-cli-rsc.h 2023-06-11 12:01:08.000000000 +0200 @@ -607,6 +607,14 @@ RSC_ISA_ADX_COMM, RSC_ISA_AES, RSC_ISA_AES_COMM, + RSC_ISA_AMX_BF16, + RSC_ISA_AMX_BF16_COMM, + RSC_ISA_AMX_TILE, + RSC_ISA_AMX_TILE_COMM, + RSC_ISA_AMX_INT8, + RSC_ISA_AMX_INT8_COMM, + RSC_ISA_AMX_FP16, + RSC_ISA_AMX_FP16_COMM, RSC_ISA_AVX, RSC_ISA_AVX_COMM, RSC_ISA_AVX512_F, @@ -627,8 +635,13 @@ RSC_ISA_AVX512_VP2I, RSC_ISA_AVX512_BF16, RSC_ISA_AVX_VEX, + RSC_ISA_AVX_INT8, + RSC_ISA_AVX_NE_CONV, RSC_ISA_AVX_128, RSC_ISA_AVX_256, + RSC_ISA_AVX_IFMA, + RSC_ISA_CMPCCXADD, + RSC_ISA_CMPCCXADD_COMM, RSC_ISA_BMI, RSC_ISA_BMI_COMM, RSC_ISA_CLWB, @@ -734,6 +747,7 @@ RSC_FEATURES_APIC, RSC_FEATURES_AVIC, RSC_FEATURES_ARAT, + RSC_FEATURES_ALTMOV, RSC_FEATURES_CLZERO, RSC_FEATURES_CORE_MP, RSC_FEATURES_CNXT_ID, @@ -758,6 +772,7 @@ RSC_FEATURES_INVLPGB, RSC_FEATURES_INVPCID, RSC_FEATURES_LM, + RSC_FEATURES_LASS, RSC_FEATURES_LAM, RSC_FEATURES_LWP, RSC_FEATURES_MBE, @@ -768,6 +783,7 @@ RSC_FEATURES_MTRR, RSC_FEATURES_NX, RSC_FEATURES_OSXSAVE, + RSC_FEATURES_OSVW, RSC_FEATURES_PAE, RSC_FEATURES_PAT, RSC_FEATURES_PBE, @@ -779,6 +795,7 @@ RSC_FEATURES_PSE36, RSC_FEATURES_PSN, RSC_FEATURES_PTWRITE, + RSC_FEATURES_PREFETCHI, RSC_FEATURES_RDT_PQE, RSC_FEATURES_RDT_PQM, RSC_FEATURES_RDPRU, @@ -788,6 +805,8 @@ RSC_FEATURES_SMAP, RSC_FEATURES_SMEP, RSC_FEATURES_ITD, + RSC_FEATURES_TBM, + RSC_FEATURES_TCE, RSC_FEATURES_TSC, RSC_FEATURES_TSC_DEADLN, RSC_FEATURES_TSXABORT, @@ -801,6 +820,7 @@ RSC_FEATURES_XD_BIT, RSC_FEATURES_XSAVE, RSC_FEATURES_XTPR, + RSC_FEATURES_XOP, RSC_FEAT_SECTION_MECH, RSC_FEAT_SECTION_SEC, RSC_TECHNOLOGIES_TITLE, @@ -1753,6 +1773,7 @@ RSC_MECH_IPRED_DIS_S, RSC_MECH_RRSBA_DIS_U, RSC_MECH_RRSBA_DIS_S, + RSC_MECH_DDPD_U_DIS, RSC_MECH_BHI_DIS_S, RSC_MECH_MCDT_NO, RSC_MECH_BTC_NO, diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-1.96.2/corefreq-cli.c new/CoreFreq-1.96.4/corefreq-cli.c --- old/CoreFreq-1.96.2/corefreq-cli.c 2023-05-31 03:08:53.000000000 +0200 +++ new/CoreFreq-1.96.4/corefreq-cli.c 2023-06-11 12:01:08.000000000 +0200 @@ -1689,6 +1689,35 @@ }, /* Row Mark */ { + (unsigned int[]) { CRC_INTEL, 0 }, + RSC(ISA_AMX_BF16).CODE(), RSC(ISA_AMX_BF16_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.ExtFeature.EDX.AMX_BF16 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.ExtFeature.EDX.AMX_BF16 }, + }, + { + (unsigned int[]) { CRC_INTEL, 0 }, + RSC(ISA_AMX_TILE).CODE(), RSC(ISA_AMX_TILE_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.ExtFeature.EDX.AMX_TILE }, + (unsigned short[]) + { RO(Shm)->Proc.Features.ExtFeature.EDX.AMX_TILE }, + }, + { + (unsigned int[]) { CRC_INTEL, 0 }, + RSC(ISA_AMX_INT8).CODE(), RSC(ISA_AMX_INT8_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.ExtFeature.EDX.AMX_INT8 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.ExtFeature.EDX.AMX_INT8 }, + }, + { + (unsigned int[]) { CRC_INTEL, 0 }, + RSC(ISA_AMX_FP16).CODE(), RSC(ISA_AMX_FP16_COMM).CODE(), + { 1, RO(Shm)->Proc.Features.ExtFeature_Leaf1_EAX.AMX_FP16 }, + (unsigned short[]) + { RO(Shm)->Proc.Features.ExtFeature_Leaf1_EAX.AMX_FP16 }, + }, +/* Row Mark */ + { NULL, RSC(ISA_AVX512_F).CODE(), NULL, { 0, RO(Shm)->Proc.Features.ExtFeature.EBX.AVX_512F }, @@ -1818,6 +1847,22 @@ (unsigned short[]) { RO(Shm)->Proc.Features.ExtFeature_Leaf1_EAX.AVX_VNNI_VEX }, }, + /* Intel ISA */ + { + (unsigned int[]) { CRC_INTEL, 0 }, + RSC(ISA_AVX_INT8).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.ExtFeature_Leaf1_EDX.AVX_VNNI_INT8}, + (unsigned short[]) + { RO(Shm)->Proc.Features.ExtFeature_Leaf1_EDX.AVX_VNNI_INT8 }, + }, + { + (unsigned int[]) { CRC_INTEL, 0 }, + RSC(ISA_AVX_NE_CONV).CODE(), NULL, + { 1,RO(Shm)->Proc.Features.ExtFeature_Leaf1_EDX.AVX_NE_CONVERT}, + (unsigned short[]) + { RO(Shm)->Proc.Features.ExtFeature_Leaf1_EDX.AVX_NE_CONVERT }, + }, + /* AMD ISA */ { (unsigned int[]) { CRC_AMD, CRC_HYGON, 0 }, RSC(ISA_AVX_128).CODE(), NULL, @@ -1832,6 +1877,21 @@ (unsigned short[]) { AVX.FP256 }, }, +/* Row Mark */ + { + (unsigned int[]) { CRC_INTEL, 0 }, + RSC(ISA_AVX_IFMA).CODE(), NULL, + { 0, RO(Shm)->Proc.Features.ExtFeature_Leaf1_EAX.AVX_IFMA }, + (unsigned short[]) + { RO(Shm)->Proc.Features.ExtFeature_Leaf1_EAX.AVX_IFMA }, + }, + { + (unsigned int[]) { CRC_INTEL, 0 }, + RSC(ISA_CMPCCXADD).CODE(), RSC(ISA_CMPCCXADD_COMM).CODE(), + { 0, RO(Shm)->Proc.Features.ExtFeature_Leaf1_EAX.CMPCCXADD }, + (unsigned short[]) + { RO(Shm)->Proc.Features.ExtFeature_Leaf1_EAX.CMPCCXADD }, + }, { (unsigned int[]) { CRC_INTEL, 0 }, RSC(ISA_MOVDIRI).CODE(), RSC(ISA_MOVDIRI_COMM).CODE(), @@ -2302,6 +2362,14 @@ }, { (unsigned int[]) { CRC_AMD, CRC_HYGON, 0 }, + RO(Shm)->Proc.Features.ExtInfo.ECX.AltMov == 1, + attr_Feat, + 2, "%s%.*sAltMov [%7s]", RSC(FEATURES_ALTMOV).CODE(), + width - 21 - RSZ(FEATURES_ALTMOV), + NULL + }, + { + (unsigned int[]) { CRC_AMD, CRC_HYGON, 0 }, RO(Shm)->Proc.Features.leaf80000008.EBX.CLZERO, attr_Feat, 2, "%s%.*sCLZERO [%7s]", RSC(FEATURES_CLZERO).CODE(), @@ -2414,12 +2482,19 @@ NULL }, { + (unsigned int[]) { CRC_AMD, CRC_HYGON, 0 }, + RO(Shm)->Proc.Features.ExtInfo.ECX.FMA4 == 1, + attr_Feat, + 2, "%s%.*sFMA4 [%7s]", RSC(FEATURES_FMA).CODE(), + width - 19 - RSZ(FEATURES_FMA), + NULL + }, + { NULL, - (RO(Shm)->Proc.Features.Std.ECX.FMA == 1) - || (RO(Shm)->Proc.Features.ExtInfo.ECX.FMA4 == 1), + RO(Shm)->Proc.Features.Std.ECX.FMA == 1, attr_Feat, - 2, "%s%.*sFMA | FMA4 [%7s]", RSC(FEATURES_FMA).CODE(), - width - 25 - RSZ(FEATURES_FMA), + 2, "%s%.*sFMA [%7s]", RSC(FEATURES_FMA).CODE(), + width - 18 - RSZ(FEATURES_FMA), NULL }, { @@ -2496,6 +2571,14 @@ }, { (unsigned int[]) { CRC_INTEL, 0 }, + RO(Shm)->Proc.Features.ExtFeature_Leaf1_EAX.LASS == 1, + attr_Feat, + 2, "%s%.*sLASS [%7s]", RSC(FEATURES_LASS).CODE(), + width - 19 - RSZ(FEATURES_LASS), + NULL + }, + { + (unsigned int[]) { CRC_INTEL, 0 }, RO(Shm)->Proc.Features.ExtFeature_Leaf1_EAX.LAM == 1, attr_Feat, 2, "%s%.*sLAM [%7s]", RSC(FEATURES_LAM).CODE(), @@ -2575,6 +2658,14 @@ NULL }, { + (unsigned int[]) { CRC_AMD, CRC_HYGON, 0 }, + RO(Shm)->Proc.Features.ExtInfo.ECX.OSVW == 1, + attr_Feat, + 2, "%s%.*sOSVW [%7s]", RSC(FEATURES_OSVW).CODE(), + width - 19 - RSZ(FEATURES_OSVW), + NULL + }, + { NULL, RO(Shm)->Proc.Features.Std.EDX.PAE == 1, attr_Feat, @@ -2665,6 +2756,14 @@ NULL }, { + (unsigned int[]) { CRC_INTEL, 0 }, + RO(Shm)->Proc.Features.ExtFeature_Leaf1_EDX.PREFETCHI == 1, + attr_Feat, + 2, "%s%.*sPREFETCHI [%7s]", RSC(FEATURES_PREFETCHI).CODE(), + width - 24 - RSZ(FEATURES_PREFETCHI), + NULL + }, + { NULL, RO(Shm)->Proc.Features.ExtFeature.EBX.PQE == 1, attr_Feat, @@ -2737,6 +2836,22 @@ NULL }, { + (unsigned int[]) { CRC_AMD, CRC_HYGON, 0 }, + RO(Shm)->Proc.Features.ExtInfo.ECX.TBM == 1, + attr_Feat, + 2, "%s%.*sTBM [%7s]", RSC(FEATURES_TBM).CODE(), + width - 18 - RSZ(FEATURES_TBM), + NULL + }, + { + (unsigned int[]) { CRC_AMD, CRC_HYGON, 0 }, + RO(Shm)->Proc.Features.ExtInfo.ECX.TCE == 1, + attr_Feat, + 2, "%s%.*sTCE [%7s]", RSC(FEATURES_TCE).CODE(), + width - 18 - RSZ(FEATURES_TCE), + NULL + }, + { NULL, RO(Shm)->Proc.Features.InvariantTSC, attr_TSC, @@ -2842,6 +2957,14 @@ width - 19 - RSZ(FEATURES_XTPR), NULL }, + { + (unsigned int[]) { CRC_AMD, CRC_HYGON, 0 }, + RO(Shm)->Proc.Features.ExtInfo.ECX.XOP == 1, + attr_Feat, + 2, "%s%.*sXOP [%7s]", RSC(FEATURES_XOP).CODE(), + width - 18 - RSZ(FEATURES_XOP), + NULL + }, /* Section Mark */ { NULL, @@ -3208,6 +3331,14 @@ MECH }, { + (unsigned int[]) { CRC_INTEL, 0 }, + RO(Shm)->Proc.Mechanisms.DDPD_U_DIS, + attr_Feat, + 2, "%s%.*sDDPD_U_DIS [%7s]", RSC(MECH_DDPD_U_DIS).CODE(), + width - 25 - RSZ(MECH_DDPD_U_DIS), + MECH + }, + { (unsigned int[]) { CRC_INTEL, 0 }, RO(Shm)->Proc.Mechanisms.BHI_DIS_S, attr_Feat, diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-1.96.2/corefreq.h new/CoreFreq-1.96.4/corefreq.h --- old/CoreFreq-1.96.2/corefreq.h 2023-05-31 03:08:53.000000000 +0200 +++ new/CoreFreq-1.96.4/corefreq.h 2023-06-11 12:01:08.000000000 +0200 @@ -81,6 +81,7 @@ IC_Z790, IC_H770, IC_B760, + IC_MTL_PCH, IC_K8, IC_ZEN, CHIPSETS @@ -392,7 +393,8 @@ BTC_NOBR : 8-6, DRAM_Scrambler : 10-8, TSME : 12-10, - _UnusedMechBits : 64-12; + DDPD_U_DIS : 14-12, + _UnusedMechBits : 64-14; } Mechanisms; enum THERMAL_FORMULAS thermalFormula; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-1.96.2/corefreqd.c new/CoreFreq-1.96.4/corefreqd.c --- old/CoreFreq-1.96.2/corefreqd.c 2023-05-31 03:08:53.000000000 +0200 +++ new/CoreFreq-1.96.4/corefreqd.c 2023-06-11 12:01:08.000000000 +0200 @@ -1849,6 +1849,10 @@ RW(Proc)->RRSBA_DIS_S, RO(Proc)->SPEC_CTRL_Mask), + DDPD_U_DIS = BITCMP_CC( LOCKLESS, + RW(Proc)->DDPD_U_DIS, + RO(Proc)->SPEC_CTRL_Mask ), + BHI_DIS_S = BITCMP_CC( LOCKLESS, RW(Proc)->BHI_DIS_S, RO(Proc)->SPEC_CTRL_Mask ); @@ -1993,6 +1997,12 @@ ); RO(Shm)->Proc.Mechanisms.RRSBA_DIS_S += (2 * RRSBA_DIS_S); + RO(Shm)->Proc.Mechanisms.DDPD_U_DIS = ( + (RO(Shm)->Proc.Features.ExtFeature.EAX.MaxSubLeaf >= 2) + && (RO(Shm)->Proc.Features.ExtFeature_Leaf2_EDX.DDPD_U_SPEC_CTRL ==1) + ); + RO(Shm)->Proc.Mechanisms.DDPD_U_DIS += (2 * DDPD_U_DIS); + RO(Shm)->Proc.Mechanisms.BHI_DIS_S = ( (RO(Shm)->Proc.Features.ExtFeature.EAX.MaxSubLeaf >= 2) && (RO(Shm)->Proc.Features.ExtFeature_Leaf2_EDX.BHI_SPEC_CTRL == 1) @@ -5772,6 +5782,9 @@ #define RPL_CAP ADL_CAP #define RPL_IMC ADL_IMC +#define MTL_CAP ADL_CAP +#define MTL_IMC ADL_IMC + void AMD_0Fh_MCH(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc)) { struct { @@ -6443,6 +6456,7 @@ [IC_Z790] = "Intel Z790", [IC_H770] = "Intel H770", [IC_B760] = "Intel B760", + [IC_MTL_PCH] = "Intel MTL PCH", [IC_K8] = "K8/HyperTransport", [IC_ZEN] = "Zen UMC" }; @@ -6973,6 +6987,13 @@ case DID_INTEL_RAPTORLAKE_B760_PCH: SET_CHIPSET(IC_B760); break; + case DID_INTEL_METEORLAKE_M_6_8_2_HB: + MTL_CAP(RO(Shm), RO(Proc), RO(Core)); + MTL_IMC(RO(Shm), RO(Proc)); + break; + case DID_INTEL_METEORLAKE_PCH: + SET_CHIPSET(IC_MTL_PCH); + break; } } diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-1.96.2/corefreqk.c new/CoreFreq-1.96.4/corefreqk.c --- old/CoreFreq-1.96.2/corefreqk.c 2023-05-31 03:08:53.000000000 +0200 +++ new/CoreFreq-1.96.4/corefreqk.c 2023-06-11 12:01:08.000000000 +0200 @@ -6591,6 +6591,38 @@ static PCI_CALLBACK AMD_DataFabric_Zeppelin(struct pci_dev *pdev) { + if (strncmp(PUBLIC(RO(Proc))->Architecture, + Arch[PUBLIC(RO(Proc))->ArchID].Architecture[CN_WHITEHAVEN], + CODENAME_LEN) == 0) + { /* Two controllers */ + return AMD_17h_DataFabric( pdev, + (const unsigned int[2][2]) { + { 0x0, 0x20}, + {0x10, 0x28} + }, + 0x30, 0x80, + 2, MC_MAX_CHA, + (const unsigned int[]) {PCI_DEVFN(0x18, 0x0), + PCI_DEVFN(0x19, 0x0)} ); + } + else if (strncmp(PUBLIC(RO(Proc))->Architecture, + Arch[PUBLIC(RO(Proc))->ArchID].Architecture[CN_NAPLES], + CODENAME_LEN) == 0) + { /* Four controllers */ + return AMD_17h_DataFabric( pdev, + (const unsigned int[2][2]) { + { 0x0, 0x20}, + {0x10, 0x28} + }, + 0x30, 0x80, + 4, MC_MAX_CHA, + (const unsigned int[]) {PCI_DEVFN(0x18, 0x0), + PCI_DEVFN(0x19, 0x0), + PCI_DEVFN(0x1a, 0x0), + PCI_DEVFN(0x1b, 0x0)} ); + } + else /* CN_SNOWY_OWL, CN_SUMMIT_RIDGE */ + { /* One controller */ return AMD_17h_DataFabric( pdev, (const unsigned int[2][2]) { { 0x0, 0x20}, @@ -6599,6 +6631,7 @@ 0x30, 0x80, 1, MC_MAX_CHA, (const unsigned int[]) {PCI_DEVFN(0x18, 0x0)} ); + } } static PCI_CALLBACK AMD_DataFabric_Raven(struct pci_dev *pdev) @@ -11314,6 +11347,7 @@ BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->IPRED_DIS_S, Core->Bind); BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->RRSBA_DIS_U, Core->Bind); BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->RRSBA_DIS_S, Core->Bind); + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->DDPD_U_DIS, Core->Bind); BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->BHI_DIS_S, Core->Bind); if (PUBLIC(RO(Proc))->Features.ExtFeature.EAX.MaxSubLeaf >= 2) @@ -11355,6 +11389,15 @@ BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->RRSBA_DIS_S, Core->Bind); } } + if (PUBLIC(RO(Proc))->Features.ExtFeature_Leaf2_EDX.DDPD_U_SPEC_CTRL) { + RDMSR(Spec_Ctrl, MSR_IA32_SPEC_CTRL); + + if (Spec_Ctrl.DDPD_U_DIS) { + BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->DDPD_U_DIS, Core->Bind); + } else { + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->DDPD_U_DIS, Core->Bind); + } + } if (PUBLIC(RO(Proc))->Features.ExtFeature_Leaf2_EDX.BHI_SPEC_CTRL) { RDMSR(Spec_Ctrl, MSR_IA32_SPEC_CTRL); @@ -11839,6 +11882,7 @@ BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->IPRED_DIS_S, Core->Bind); BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->RRSBA_DIS_U, Core->Bind); BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->RRSBA_DIS_S, Core->Bind); + BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->DDPD_U_DIS, Core->Bind); BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->BHI_DIS_S , Core->Bind); BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->BTC_NOBR , Core->Bind); diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-1.96.2/corefreqk.h new/CoreFreq-1.96.4/corefreqk.h --- old/CoreFreq-1.96.2/corefreqk.h 2023-05-31 03:08:53.000000000 +0200 +++ new/CoreFreq-1.96.4/corefreqk.h 2023-06-11 12:01:08.000000000 +0200 @@ -1309,6 +1309,11 @@ = {.func = 0x80000020, .sub = 0x00000000}, [CPUID_80000020_00000001_MBE_SUB_LEAF] = {.func = 0x80000020, .sub = 0x00000001}, +/* AMD Family 19h Model 11h, Revision B1 */ + [CPUID_80000020_00000002_SMBE_SUB_LEAF] + = {.func = 0x80000020, .sub = 0x00000002}, + [CPUID_80000020_00000003_BMEC_SUB_LEAF] + = {.func = 0x80000020, .sub = 0x00000003}, /* AMD Family 19h */ [CPUID_80000021_00000000_EXTENDED_FEATURE_2] = {.func = 0x80000021, .sub = 0x00000000}, @@ -2074,6 +2079,8 @@ static PCI_CALLBACK GLK_IMC(struct pci_dev *dev) ; #define RPL_IMC ADL_IMC #define RPL_PCH CML_PCH +#define MTL_IMC ADL_IMC +#define MTL_PCH CML_PCH static PCI_CALLBACK AMD_0Fh_MCH(struct pci_dev *dev) ; static PCI_CALLBACK AMD_0Fh_HTT(struct pci_dev *dev) ; static PCI_CALLBACK AMD_Zen_IOMMU(struct pci_dev *dev) ; @@ -2983,6 +2990,19 @@ {0, } }; +/* Meteor Lake */ +static struct pci_device_id PCI_MTL_ids[] = { + { + PCI_VDEVICE(INTEL, DID_INTEL_METEORLAKE_M_6_8_2_HB), + .driver_data = (kernel_ulong_t) MTL_IMC + }, + { + PCI_VDEVICE(INTEL, DID_INTEL_METEORLAKE_PCH), + .driver_data = (kernel_ulong_t) MTL_PCH + }, + {0, } +}; + /* AMD Family 0Fh */ static struct pci_device_id PCI_AMD_0Fh_ids[] = { { @@ -10320,7 +10340,7 @@ [Meteorlake_M] = { /* 83*/ .Signature = _Meteorlake_M, .Query = Query_Skylake, - .Update = PerCore_Skylake_Query, + .Update = PerCore_Kaby_Lake_Query, .Start = Start_Alderlake, .Stop = Stop_Alderlake, .Exit = NULL, @@ -10329,12 +10349,12 @@ .ClockMod = ClockMod_Skylake_HWP, .TurboClock = Intel_Turbo_Config8C, .thermalFormula = THERMAL_FORMULA_INTEL, - .voltageFormula = VOLTAGE_FORMULA_INTEL_SNB, + .voltageFormula = VOLTAGE_FORMULA_INTEL_SAV, .powerFormula = POWER_FORMULA_INTEL, - .PCI_ids = PCI_Void_ids, + .PCI_ids = PCI_MTL_ids, .Uncore = { - .Start = NULL, - .Stop = NULL, + .Start = Start_Uncore_Alderlake, + .Stop = Stop_Uncore_Alderlake, .ClockMod = Haswell_Uncore_Ratio }, .Specific = Void_Specific, @@ -10344,7 +10364,7 @@ [Meteorlake_N] = { /* 84*/ .Signature = _Meteorlake_N, .Query = Query_Skylake, - .Update = PerCore_Skylake_Query, + .Update = PerCore_Kaby_Lake_Query, .Start = Start_Alderlake, .Stop = Stop_Alderlake, .Exit = NULL, @@ -10353,12 +10373,12 @@ .ClockMod = ClockMod_Skylake_HWP, .TurboClock = Intel_Turbo_Config8C, .thermalFormula = THERMAL_FORMULA_INTEL, - .voltageFormula = VOLTAGE_FORMULA_INTEL_SNB, + .voltageFormula = VOLTAGE_FORMULA_INTEL_SAV, .powerFormula = POWER_FORMULA_INTEL, - .PCI_ids = PCI_Void_ids, + .PCI_ids = PCI_MTL_ids, .Uncore = { - .Start = NULL, - .Stop = NULL, + .Start = Start_Uncore_Alderlake, + .Stop = Stop_Uncore_Alderlake, .ClockMod = Haswell_Uncore_Ratio }, .Specific = Void_Specific, @@ -10368,7 +10388,7 @@ [Meteorlake_S] = { /* 85*/ .Signature = _Meteorlake_S, .Query = Query_Skylake, - .Update = PerCore_Skylake_Query, + .Update = PerCore_Kaby_Lake_Query, .Start = Start_Alderlake, .Stop = Stop_Alderlake, .Exit = NULL, @@ -10377,18 +10397,19 @@ .ClockMod = ClockMod_Skylake_HWP, .TurboClock = Intel_Turbo_Config8C, .thermalFormula = THERMAL_FORMULA_INTEL, - .voltageFormula = VOLTAGE_FORMULA_INTEL_SNB, + .voltageFormula = VOLTAGE_FORMULA_INTEL_SAV, .powerFormula = POWER_FORMULA_INTEL, - .PCI_ids = PCI_Void_ids, + .PCI_ids = PCI_MTL_ids, .Uncore = { - .Start = NULL, - .Stop = NULL, + .Start = Start_Uncore_Alderlake, + .Stop = Stop_Uncore_Alderlake, .ClockMod = Haswell_Uncore_Ratio }, .Specific = Void_Specific, .SystemDriver = SKL_Driver, .Architecture = Arch_Meteorlake_S }, + [Raptorlake] = { /* 86*/ .Signature = _Raptorlake, .Query = Query_Skylake, diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-1.96.2/coretypes.h new/CoreFreq-1.96.4/coretypes.h --- old/CoreFreq-1.96.2/coretypes.h 2023-05-31 03:08:53.000000000 +0200 +++ new/CoreFreq-1.96.4/coretypes.h 2023-06-11 12:01:08.000000000 +0200 @@ -6,7 +6,7 @@ #define COREFREQ_MAJOR 1 #define COREFREQ_MINOR 96 -#define COREFREQ_REV 2 +#define COREFREQ_REV 4 #if !defined(CORE_COUNT) #define CORE_COUNT 256 @@ -1006,6 +1006,9 @@ CPUID_8000001F_00000000_SECURE_ENCRYPTION, CPUID_80000020_00000000_MBE_SUB_LEAF, CPUID_80000020_00000001_MBE_SUB_LEAF, +/* AMD Family 19h Model 11h, Revision B1 */ + CPUID_80000020_00000002_SMBE_SUB_LEAF, + CPUID_80000020_00000003_BMEC_SUB_LEAF, /* AMD Family 19h */ CPUID_80000021_00000000_EXTENDED_FEATURE_2, CPUID_80000022_00000000_EXT_PERF_MON_DEBUG, @@ -1226,7 +1229,8 @@ HWP_Idle : 21-20,/* Ignore (or not) Idle SMT Processor */ Reserved3 : 23-21, ITD_MSR : 24-23, /* HW_FEEDBACK_{CHAR,THREAD_CONFIG} */ - Reserved4 : 32-24; + THERM_INT_MSR : 25-24, /* IA32_THERM_INTERRUPT MSR */ + Reserved4 : 32-25; } EAX; struct { /* Intel reserved. */ @@ -1330,9 +1334,9 @@ MAWAU : 22-17, /* for BNDLDX & BNDSTX instructions*/ RDPID : 23-22, /* Intel RDPID inst. & IA32_TSC_AUX */ KL : 24-23, /* Key Locker */ - Reserved2 : 25-24, + BUS_LOCK_DETECT : 25-24, CLDEMOTE : 26-25, /* Support of cache line demote */ - Reserved3 : 27-26, + Reserved2 : 27-26, MOVDIRI : 28-27, /* Move Doubleword as Direct Store*/ MOVDIR64B : 29-28, /* Move 64 Bytes as Direct Store*/ ENQCMD : 30-29, /* Support of Enqueue Stores */ @@ -1342,7 +1346,8 @@ struct { /* Intel reserved. */ unsigned int - Reserved1 : 2-0, + Reserved1 : 1-0, + SGX_KEYS : 2-1, AVX512_4VNNIW : 3-2, /* Intel Xeon Phi */ AVX512_4FMAPS : 4-3, /* Intel Xeon Phi */ FSRM : 5-4, /* Fast Short REP MOVSB */ @@ -1361,7 +1366,11 @@ PCONFIG : 19-18, ArchitecturalLBRs:20-19, CET_IBT : 21-20, /* CET Indirect Branch Tracking */ - Reserved5 : 26-21, + Reserved5 : 22-21, + AMX_BF16 : 23-22, + AVX512_FP16 : 24-23, + AMX_TILE : 25-24, + AMX_INT8 : 26-25, IBRS_IBPB_Cap : 27-26, /* IA32_SPEC_CTRL,IA32_PRED_CMD */ STIBP_Cap : 28-27, /* IA32_SPEC_CTRL[1] */ L1D_FLUSH_Cap : 29-28, /* IA32_FLUSH_CMD */ @@ -1380,23 +1389,23 @@ RAO_INT : 4-3, /* Grand Ridge */ AVX_VNNI_VEX : 5-4, /* Vector Neural Network Instructions*/ AVX512_BF16 : 6-5, /* BFLOAT16 support in AVX512 */ - Reserved2 : 7-6, + LASS : 7-6, CMPCCXADD : 8-7, /* Sierra Forest, Grand Ridge */ ArchPerfmonExt : 9-8, - Reserved3 : 10-9, + Reserved2 : 10-9, FZRM : 11-10, /* Fast Zero-length REP MOVSB */ FSRS : 12-11, /* Fast Short REP STOSB:Store String */ FSRC : 13-12, /* Fast Short REP CMPSB, REP SCASB */ - Reserved4 : 19-13, + Reserved3 : 19-13, WRMSRNS : 20-19, /* Sierra Forest, Grand Ridge */ - Reserved5 : 21-20, + Reserved4 : 21-20, AMX_FP16 : 22-21, /* Granite Rapids */ HRESET : 23-22, /* History Reset instruction */ AVX_IFMA : 24-23, /* Sierra Forest, Grand Ridge */ - Reserved6 : 26-24, + Reserved5 : 26-24, LAM : 27-26, /* Linear Address Masking */ RDMSRLIST : 28-27, /* Sierra Forest, Grand Ridge */ - Reserved7 : 32-28; + Reserved6 : 32-28; } EAX; struct { @@ -1416,8 +1425,10 @@ AVX_VNNI_INT8 : 5-4, /* Sierra Forest, Grand Ridge */ AVX_NE_CONVERT : 6-5, /* Sierra Forest, Grand Ridge */ Reserved2 : 14-6, - PREFETCHITI : 15-14, /* Granite Rapids: IA32_UINTR */ - Reserved3 : 32-15; + PREFETCHI : 15-14, /* Granite Rapids: IA32_UINTR */ + Reserved3 : 18-15, + CET_SSS : 19-18, + Reserved4 : 32-19; } EDX; } CPUID_0x00000007_1; @@ -1434,10 +1445,10 @@ PSFD_SPEC_CTRL : 1-0, IPRED_SPEC_CTRL : 2-1, RRSBA_SPEC_CTRL : 3-2, - Reserved1 : 4-3, + DDPD_U_SPEC_CTRL: 4-3, BHI_SPEC_CTRL : 5-4, MCDT_NO : 6-5, - Reserved2 : 32-6; + Reserved : 32-6; } EDX; } CPUID_0x00000007_2; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-1.96.2/intel_reg.h new/CoreFreq-1.96.4/intel_reg.h --- old/CoreFreq-1.96.2/intel_reg.h 2023-05-31 03:08:53.000000000 +0200 +++ new/CoreFreq-1.96.4/intel_reg.h 2023-06-11 12:01:08.000000000 +0200 @@ -473,9 +473,10 @@ RRSBA_DIS_U : 6-5, /* CPUID(EAX=07H,ECX=2):EDX[ 2] == 1 */ RRSBA_DIS_S : 7-6, /* CPUID(EAX=07H,ECX=2):EDX[ 2] == 1 */ PSFD : 8-7, /* CPUID(EAX=07H,ECX=2):EDX[ 0] == 1 */ - ReservedBits1 : 10-8, + DDPD_U_DIS : 9-8, /* CPUID(EAX=07H,ECX=2):EDX[ 3] == 1 */ + ReservedBits1 : 10-9, BHI_DIS_S : 11-10, /* CPUID(EAX=07H,ECX=2):EDX[ 4] == 1 */ - ReservedBits : 64-11; + ReservedBits2 : 64-11; }; } SPEC_CTRL;
