MYNEWT-581; kernel/os - deal with extended frames when calculating sp for corefile.
Project: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/repo Commit: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/commit/f5d48ad6 Tree: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/tree/f5d48ad6 Diff: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/diff/f5d48ad6 Branch: refs/heads/develop Commit: f5d48ad634a01294757b88d27aa213e7bf9ddaeb Parents: 522d97b Author: Marko Kiiskila <ma...@runtime.io> Authored: Tue Feb 7 17:53:10 2017 -0800 Committer: Marko Kiiskila <ma...@runtime.io> Committed: Tue Feb 7 17:53:10 2017 -0800 ---------------------------------------------------------------------- kernel/os/src/arch/cortex_m4/os_fault.c | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) ---------------------------------------------------------------------- http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/f5d48ad6/kernel/os/src/arch/cortex_m4/os_fault.c ---------------------------------------------------------------------- diff --git a/kernel/os/src/arch/cortex_m4/os_fault.c b/kernel/os/src/arch/cortex_m4/os_fault.c index 8bd881f..f1ddc00 100644 --- a/kernel/os/src/arch/cortex_m4/os_fault.c +++ b/kernel/os/src/arch/cortex_m4/os_fault.c @@ -6,7 +6,7 @@ * to you under the Apache License, Version 2.0 (the * "License"); you may not use this file except in compliance * with the License. You may obtain a copy of the License at - * + * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, @@ -93,14 +93,26 @@ trap_to_coredump(struct trap_frame *tf, struct coredump_regs *regs) /* * SP just before exception for the coredump. * See ARMv7-M Architecture Ref Manual, sections B1.5.6 - B1.5.8 - * SP is adjusted by 0x20. - * If SCB->CCR.STKALIGN is set, SP is aligned to 8-byte boundary on - * exception entry. + * If floating point registers were pushed to stack, SP is adjusted + * by 0x68. + * Otherwise, SP is adjusted by 0x20. + * If SCB->CCR.STKALIGN is set, or fpu is active, SP is aligned to + * 8-byte boundary on exception entry. * If this alignment adjustment happened, xPSR will have bit 9 set. */ - regs->sp = ((uint32_t)tf->ef) + 0x20; - if ((SCB->CCR & SCB_CCR_STKALIGN_Msk) & tf->ef->psr & (1 << 9)) { - regs->sp += 4; + if ((tf->lr & 0x10) == 0) { + /* + * Extended frame + */ + regs->sp = ((uint32_t)tf->ef) + 0x68; + if (tf->ef->psr & (1 << 9)) { + regs->sp += 4; + } + } else { + regs->sp = ((uint32_t)tf->ef) + 0x20; + if ((SCB->CCR & SCB_CCR_STKALIGN_Msk) & tf->ef->psr & (1 << 9)) { + regs->sp += 4; + } } regs->lr = tf->ef->lr; regs->pc = tf->ef->pc;
