Add support for STM32F7xx and NUCLEO-F767
Project: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/repo Commit: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/commit/35529b95 Tree: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/tree/35529b95 Diff: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/diff/35529b95 Branch: refs/heads/develop Commit: 35529b95f049cd1d83c67a986bd0510dabcce357 Parents: 331f6c5 Author: Fabio Utzig <ut...@utzig.org> Authored: Wed Feb 15 13:57:01 2017 -0800 Committer: Fabio Utzig <ut...@utzig.org> Committed: Fri Mar 10 16:47:06 2017 -0300 ---------------------------------------------------------------------- compiler/arm-none-eabi-m7/compiler.yml | 2 +- hw/bsp/stm32f767-nucleo/_f407.cfg | 82 + .../stm32f767-nucleo/boot-stm32f767-nucleo.ld | 30 + hw/bsp/stm32f767-nucleo/bsp.yml | 61 + hw/bsp/stm32f767-nucleo/include/bsp/bsp.h | 61 + .../stm32f767-nucleo/include/bsp/cmsis_nvic.h | 29 + .../include/bsp/stm32f7xx_hal_conf.h | 446 + hw/bsp/stm32f767-nucleo/nucleo767.cfg | 22 + hw/bsp/stm32f767-nucleo/nucleo767_debug.sh | 37 + hw/bsp/stm32f767-nucleo/nucleo767_download.sh | 41 + hw/bsp/stm32f767-nucleo/pkg.yml | 40 + .../src/arch/cortex_m7/startup_stm32f767xx.s | 652 + hw/bsp/stm32f767-nucleo/src/hal_bsp.c | 133 + hw/bsp/stm32f767-nucleo/src/sbrk.c | 50 + hw/bsp/stm32f767-nucleo/src/system_stm32f7xx.c | 277 + hw/bsp/stm32f767-nucleo/stm32f767-nucleo.ld | 32 + hw/bsp/stm32f767-nucleo/syscfg.yml | 38 + hw/mcu/stm/stm32f7xx/include/mcu/cortex_m7.h | 35 + hw/mcu/stm/stm32f7xx/include/mcu/mcu.h | 48 + hw/mcu/stm/stm32f7xx/include/mcu/stm32f7_bsp.h | 55 + .../include/mcu/stm32f7xx_mynewt_hal.h | 74 + hw/mcu/stm/stm32f7xx/pkg.yml | 40 + .../Device/ST/STM32F7xx/Include/stm32f722xx.h | 15165 ++++++++++++ .../Device/ST/STM32F7xx/Include/stm32f723xx.h | 15244 ++++++++++++ .../Device/ST/STM32F7xx/Include/stm32f732xx.h | 15390 ++++++++++++ .../Device/ST/STM32F7xx/Include/stm32f733xx.h | 15469 ++++++++++++ .../Device/ST/STM32F7xx/Include/stm32f745xx.h | 17219 +++++++++++++ .../Device/ST/STM32F7xx/Include/stm32f746xx.h | 17569 +++++++++++++ .../Device/ST/STM32F7xx/Include/stm32f756xx.h | 17856 +++++++++++++ .../Device/ST/STM32F7xx/Include/stm32f765xx.h | 17938 ++++++++++++++ .../Device/ST/STM32F7xx/Include/stm32f767xx.h | 18599 ++++++++++++++ .../Device/ST/STM32F7xx/Include/stm32f769xx.h | 21769 ++++++++++++++++ .../Device/ST/STM32F7xx/Include/stm32f777xx.h | 18886 ++++++++++++++ .../Device/ST/STM32F7xx/Include/stm32f779xx.h | 22056 +++++++++++++++++ .../Device/ST/STM32F7xx/Include/stm32f7xx.h | 230 + .../ST/STM32F7xx/Include/system_stm32f7xx.h | 125 + .../Device/ST/STM32F7xx/Release_Notes.html | 191 + .../Source/Templates/arm/startup_stm32f722xx.s | 463 + .../Source/Templates/arm/startup_stm32f723xx.s | 463 + .../Source/Templates/arm/startup_stm32f732xx.s | 465 + .../Source/Templates/arm/startup_stm32f733xx.s | 465 + .../Source/Templates/arm/startup_stm32f745xx.s | 481 + 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.../Source/Templates/gcc/startup_stm32f779xx.s | 642 + .../iar/linker/stm32f722xx_ITCM_flash.icf | 35 + .../Templates/iar/linker/stm32f722xx_flash.icf | 34 + .../Templates/iar/linker/stm32f722xx_sram.icf | 34 + .../iar/linker/stm32f723xx_ITCM_flash.icf | 35 + .../Templates/iar/linker/stm32f723xx_flash.icf | 34 + .../Templates/iar/linker/stm32f723xx_sram.icf | 34 + .../iar/linker/stm32f732xx_ITCM_flash.icf | 35 + .../Templates/iar/linker/stm32f732xx_flash.icf | 34 + .../Templates/iar/linker/stm32f732xx_sram.icf | 34 + .../iar/linker/stm32f733xx_ITCM_flash.icf | 35 + .../Templates/iar/linker/stm32f733xx_flash.icf | 34 + .../Templates/iar/linker/stm32f733xx_sram.icf | 34 + .../iar/linker/stm32f745xx_ITCM_flash.icf | 35 + .../Templates/iar/linker/stm32f745xx_flash.icf | 34 + .../Templates/iar/linker/stm32f745xx_sram.icf | 34 + .../iar/linker/stm32f746xx_ITCM_flash.icf | 35 + .../Templates/iar/linker/stm32f746xx_flash.icf | 34 + .../Templates/iar/linker/stm32f746xx_sram.icf | 34 + .../iar/linker/stm32f756xx_ITCM_flash.icf | 35 + .../Templates/iar/linker/stm32f756xx_flash.icf | 34 + .../Templates/iar/linker/stm32f756xx_sram.icf | 34 + .../iar/linker/stm32f765xx_ITCM_flash.icf | 35 + .../Templates/iar/linker/stm32f765xx_flash.icf | 34 + .../Templates/iar/linker/stm32f765xx_sram.icf | 34 + .../iar/linker/stm32f767xx_ITCM_flash.icf | 35 + .../Templates/iar/linker/stm32f767xx_flash.icf | 34 + .../Templates/iar/linker/stm32f767xx_sram.icf | 34 + .../iar/linker/stm32f769xx_ITCM_flash.icf | 35 + .../Templates/iar/linker/stm32f769xx_flash.icf | 34 + .../Templates/iar/linker/stm32f769xx_sram.icf | 34 + .../iar/linker/stm32f777xx_ITCM_flash.icf | 35 + .../Templates/iar/linker/stm32f777xx_flash.icf | 34 + .../Templates/iar/linker/stm32f777xx_sram.icf | 34 + .../iar/linker/stm32f779xx_ITCM_flash.icf | 35 + .../Templates/iar/linker/stm32f779xx_flash.icf | 34 + .../Templates/iar/linker/stm32f779xx_sram.icf | 34 + .../Source/Templates/iar/startup_stm32f722xx.s | 668 + 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.../Inc/stm32f7xx_hal_cortex.h | 424 + .../Inc/stm32f7xx_hal_crc.h | 423 + .../Inc/stm32f7xx_hal_crc_ex.h | 168 + .../Inc/stm32f7xx_hal_cryp.h | 1168 + .../Inc/stm32f7xx_hal_cryp_ex.h | 293 + .../Inc/stm32f7xx_hal_dac.h | 408 + .../Inc/stm32f7xx_hal_dac_ex.h | 191 + .../Inc/stm32f7xx_hal_dcmi.h | 628 + .../Inc/stm32f7xx_hal_dcmi_ex.h | 55 + .../Inc/stm32f7xx_hal_def.h | 213 + .../Inc/stm32f7xx_hal_dfsdm.h | 710 + .../Inc/stm32f7xx_hal_dma.h | 768 + .../Inc/stm32f7xx_hal_dma2d.h | 638 + .../Inc/stm32f7xx_hal_dma_ex.h | 203 + .../Inc/stm32f7xx_hal_dsi.h | 1242 + .../Inc/stm32f7xx_hal_eth.h | 2184 ++ .../Inc/stm32f7xx_hal_flash.h | 426 + .../Inc/stm32f7xx_hal_flash_ex.h | 663 + .../Inc/stm32f7xx_hal_gpio.h | 327 + .../Inc/stm32f7xx_hal_gpio_ex.h | 675 + .../Inc/stm32f7xx_hal_hash.h | 450 + .../Inc/stm32f7xx_hal_hash_ex.h | 199 + .../Inc/stm32f7xx_hal_hcd.h | 281 + .../Inc/stm32f7xx_hal_i2c.h | 710 + .../Inc/stm32f7xx_hal_i2c_ex.h | 223 + .../Inc/stm32f7xx_hal_i2s.h | 483 + .../Inc/stm32f7xx_hal_irda.h | 760 + .../Inc/stm32f7xx_hal_irda_ex.h | 239 + .../Inc/stm32f7xx_hal_iwdg.h | 257 + .../Inc/stm32f7xx_hal_jpeg.h | 581 + .../Inc/stm32f7xx_hal_lptim.h | 739 + .../Inc/stm32f7xx_hal_ltdc.h | 662 + .../Inc/stm32f7xx_hal_ltdc_ex.h | 151 + .../Inc/stm32f7xx_hal_mdios.h | 537 + .../Inc/stm32f7xx_hal_mmc.h | 695 + .../Inc/stm32f7xx_hal_nand.h | 336 + .../Inc/stm32f7xx_hal_nor.h | 299 + .../Inc/stm32f7xx_hal_pcd.h | 337 + .../Inc/stm32f7xx_hal_pcd_ex.h | 116 + .../Inc/stm32f7xx_hal_pwr.h | 422 + .../Inc/stm32f7xx_hal_pwr_ex.h | 280 + .../Inc/stm32f7xx_hal_qspi.h | 781 + .../Inc/stm32f7xx_hal_rcc.h | 1306 + .../Inc/stm32f7xx_hal_rcc_ex.h | 3519 +++ .../Inc/stm32f7xx_hal_rng.h | 358 + .../Inc/stm32f7xx_hal_rtc.h | 813 + .../Inc/stm32f7xx_hal_rtc_ex.h | 1035 + .../Inc/stm32f7xx_hal_sai.h | 850 + .../Inc/stm32f7xx_hal_sai_ex.h | 56 + .../STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h | 716 + .../Inc/stm32f7xx_hal_sdram.h | 199 + .../Inc/stm32f7xx_hal_smartcard.h | 949 + .../Inc/stm32f7xx_hal_smartcard_ex.h | 308 + .../Inc/stm32f7xx_hal_smbus.h | 697 + .../Inc/stm32f7xx_hal_spdifrx.h | 560 + .../Inc/stm32f7xx_hal_spi.h | 689 + .../Inc/stm32f7xx_hal_sram.h | 195 + .../Inc/stm32f7xx_hal_tim.h | 1563 ++ .../Inc/stm32f7xx_hal_tim_ex.h | 648 + .../Inc/stm32f7xx_hal_uart.h | 1221 + .../Inc/stm32f7xx_hal_uart_ex.h | 365 + .../Inc/stm32f7xx_hal_usart.h | 696 + .../Inc/stm32f7xx_hal_usart_ex.h | 158 + .../Inc/stm32f7xx_hal_wwdg.h | 285 + .../STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_adc.h | 4767 ++++ .../STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h | 1994 ++ .../Inc/stm32f7xx_ll_cortex.h | 657 + .../STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_crc.h | 479 + .../STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dac.h | 1316 + .../STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h | 2911 +++ .../Inc/stm32f7xx_ll_dma2d.h | 2070 ++ .../Inc/stm32f7xx_ll_exti.h | 968 + .../STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h | 1339 + .../Inc/stm32f7xx_ll_gpio.h | 1000 + .../STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_i2c.h | 2207 ++ .../Inc/stm32f7xx_ll_iwdg.h | 363 + .../Inc/stm32f7xx_ll_lptim.h | 1382 ++ .../STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h | 1036 + .../STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h | 5170 ++++ .../STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rng.h | 355 + .../STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rtc.h | 3867 +++ .../Inc/stm32f7xx_ll_sdmmc.h | 1024 + .../STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h | 2293 ++ .../Inc/stm32f7xx_ll_system.h | 1039 + .../STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h | 4663 ++++ .../Inc/stm32f7xx_ll_usart.h | 3560 +++ .../STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usb.h | 474 + .../Inc/stm32f7xx_ll_utils.h | 323 + .../Inc/stm32f7xx_ll_wwdg.h | 342 + .../STM32F7xx_HAL_Driver/Release_Notes.html | 1028 + .../STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c | 536 + .../Src/stm32f7xx_hal_adc.c | 1686 ++ .../Src/stm32f7xx_hal_adc_ex.c | 1069 + .../Src/stm32f7xx_hal_can.c | 1412 ++ .../Src/stm32f7xx_hal_cec.c | 670 + .../Src/stm32f7xx_hal_cortex.c | 523 + .../Src/stm32f7xx_hal_crc.c | 531 + .../Src/stm32f7xx_hal_crc_ex.c | 242 + .../Src/stm32f7xx_hal_cryp.c | 5182 ++++ .../Src/stm32f7xx_hal_cryp_ex.c | 6039 +++++ .../Src/stm32f7xx_hal_dac.c | 967 + .../Src/stm32f7xx_hal_dac_ex.c | 388 + .../Src/stm32f7xx_hal_dcmi.c | 906 + .../Src/stm32f7xx_hal_dcmi_ex.c | 52 + .../Src/stm32f7xx_hal_dfsdm.c | 3018 +++ .../Src/stm32f7xx_hal_dma.c | 1318 + .../Src/stm32f7xx_hal_dma2d.c | 1764 ++ .../Src/stm32f7xx_hal_dma_ex.c | 328 + .../Src/stm32f7xx_hal_dsi.c | 2262 ++ .../Src/stm32f7xx_hal_eth.c | 2045 ++ .../Src/stm32f7xx_hal_flash.c | 829 + .../Src/stm32f7xx_hal_flash_ex.c | 1140 + .../Src/stm32f7xx_hal_gpio.c | 543 + .../Src/stm32f7xx_hal_hash.c | 1878 ++ .../Src/stm32f7xx_hal_hash_ex.c | 1636 ++ .../Src/stm32f7xx_hal_hcd.c | 1229 + .../Src/stm32f7xx_hal_i2c.c | 4867 ++++ .../Src/stm32f7xx_hal_i2c_ex.c | 275 + .../Src/stm32f7xx_hal_i2s.c | 1556 ++ .../Src/stm32f7xx_hal_irda.c | 2240 ++ .../Src/stm32f7xx_hal_iwdg.c | 282 + .../Src/stm32f7xx_hal_jpeg.c | 3460 +++ .../Src/stm32f7xx_hal_lptim.c | 1705 ++ .../Src/stm32f7xx_hal_ltdc.c | 1915 ++ .../Src/stm32f7xx_hal_ltdc_ex.c | 162 + .../Src/stm32f7xx_hal_mdios.c | 627 + .../Src/stm32f7xx_hal_mmc.c | 2493 ++ .../Src/stm32f7xx_hal_msp_template.c | 119 + .../Src/stm32f7xx_hal_nand.c | 1859 ++ .../Src/stm32f7xx_hal_nor.c | 1044 + .../Src/stm32f7xx_hal_pcd.c | 1311 + .../Src/stm32f7xx_hal_pcd_ex.c | 322 + .../Src/stm32f7xx_hal_pwr.c | 609 + .../Src/stm32f7xx_hal_pwr_ex.c | 572 + .../Src/stm32f7xx_hal_qspi.c | 2337 ++ .../Src/stm32f7xx_hal_rcc.c | 1130 + .../Src/stm32f7xx_hal_rcc_ex.c | 1602 ++ .../Src/stm32f7xx_hal_rng.c | 522 + .../Src/stm32f7xx_hal_rtc.c | 1567 ++ .../Src/stm32f7xx_hal_rtc_ex.c | 1853 ++ .../Src/stm32f7xx_hal_sai.c | 2184 ++ .../Src/stm32f7xx_hal_sai_ex.c | 52 + .../STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c | 2913 +++ .../Src/stm32f7xx_hal_sdram.c | 859 + .../Src/stm32f7xx_hal_smartcard.c | 2282 ++ .../Src/stm32f7xx_hal_smartcard_ex.c | 184 + .../Src/stm32f7xx_hal_smbus.c | 2053 ++ .../Src/stm32f7xx_hal_spdifrx.c | 1258 + .../Src/stm32f7xx_hal_spi.c | 3739 +++ .../Src/stm32f7xx_hal_sram.c | 690 + .../Src/stm32f7xx_hal_tim.c | 5534 +++++ .../Src/stm32f7xx_hal_tim_ex.c | 2565 ++ .../stm32f7xx_hal_timebase_rtc_alarm_template.c | 314 + ...stm32f7xx_hal_timebase_rtc_wakeup_template.c | 293 + .../Src/stm32f7xx_hal_timebase_tim_template.c | 184 + .../Src/stm32f7xx_hal_uart.c | 2174 ++ .../Src/stm32f7xx_hal_usart.c | 1986 ++ .../Src/stm32f7xx_hal_wwdg.c | 322 + .../STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_adc.c | 920 + .../STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_crc.c | 125 + .../STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dac.c | 273 + .../STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c | 464 + .../Src/stm32f7xx_ll_dma2d.c | 653 + .../Src/stm32f7xx_ll_exti.c | 232 + .../STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c | 1117 + .../Src/stm32f7xx_ll_gpio.c | 325 + .../STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_i2c.c | 258 + .../Src/stm32f7xx_ll_lptim.c | 212 + .../STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_pwr.c | 105 + .../STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c | 1581 ++ .../STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rng.c | 116 + .../STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rtc.c | 897 + .../Src/stm32f7xx_ll_sdmmc.c | 1504 ++ .../STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c | 589 + .../STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c | 1396 ++ .../Src/stm32f7xx_ll_usart.c | 463 + .../STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usb.c | 1797 ++ .../Src/stm32f7xx_ll_utils.c | 757 + hw/mcu/stm/stm32f7xx/src/hal_flash.c | 141 + hw/mcu/stm/stm32f7xx/src/hal_gpio.c | 715 + hw/mcu/stm/stm32f7xx/src/hal_i2c.c | 177 + hw/mcu/stm/stm32f7xx/src/hal_os_tick.c | 55 + hw/mcu/stm/stm32f7xx/src/hal_reset_cause.c | 47 + hw/mcu/stm/stm32f7xx/src/hal_system.c | 55 + hw/mcu/stm/stm32f7xx/src/hal_system_start.c | 54 + hw/mcu/stm/stm32f7xx/src/hal_timer.c | 648 + hw/mcu/stm/stm32f7xx/src/hal_uart.c | 428 + hw/mcu/stm/stm32f7xx/src/hal_watchdog.c | 59 + hw/mcu/stm/stm32f7xx/src/stm32f7xx_hw_id.c | 42 + hw/mcu/stm/stm32f7xx/stm32f767.ld | 212 + hw/scripts/common.sh | 7 +- hw/scripts/openocd.sh | 64 +- .../os/include/os/arch/cortex_m7/os/os_arch.h | 84 + kernel/os/src/arch/cortex_m7/m7/HAL_CM7.s | 240 + kernel/os/src/arch/cortex_m7/m7/SVC_Table.s | 56 + kernel/os/src/arch/cortex_m7/os_arch_arm.c | 352 + kernel/os/src/arch/cortex_m7/os_fault.c | 176 + 315 files changed, 450953 insertions(+), 37 deletions(-) ---------------------------------------------------------------------- http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/35529b95/compiler/arm-none-eabi-m7/compiler.yml ---------------------------------------------------------------------- diff --git a/compiler/arm-none-eabi-m7/compiler.yml b/compiler/arm-none-eabi-m7/compiler.yml index bf69c45..cac9728 100644 --- a/compiler/arm-none-eabi-m7/compiler.yml +++ b/compiler/arm-none-eabi-m7/compiler.yml @@ -28,7 +28,7 @@ compiler.path.objcopy: arm-none-eabi-objcopy compiler.flags.base: -mcpu=cortex-m7 -mthumb-interwork -mthumb -Wall -Werror -fno-exceptions -ffunction-sections -fdata-sections compiler.flags.default: [compiler.flags.base, -O1 -ggdb] compiler.flags.optimized: [compiler.flags.base, -Os -ggdb] -compiler.flags.debug: [compiler.flags.base, -O1 -ggdb] +compiler.flags.debug: [compiler.flags.base, -O0 -ggdb -fomit-frame-pointer] compiler.as.flags: [-x, assembler-with-cpp] http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/35529b95/hw/bsp/stm32f767-nucleo/_f407.cfg ---------------------------------------------------------------------- diff --git a/hw/bsp/stm32f767-nucleo/_f407.cfg b/hw/bsp/stm32f767-nucleo/_f407.cfg new file mode 100644 index 0000000..7c46d8b --- /dev/null +++ b/hw/bsp/stm32f767-nucleo/_f407.cfg @@ -0,0 +1,82 @@ +# +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# + +# script for stm32f4x family + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32f4x +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +# Work-area is a space in RAM used for flash programming +# By default use 64kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x10000 +} + +# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz +# +# Since we may be running of an RC oscilator, we crank down the speed a +# bit more to be on the safe side. Perhaps superstition, but if are +# running off a crystal, we can run closer to the limit. Note +# that there can be a pretty wide band where things are more or less stable. +adapter_khz 1000 + +adapter_nsrst_delay 100 +jtag_ntrst_delay 100 + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + # See STM Document RM0090 + # Section 32.6.2 - corresponds to Cortex-M4 r0p1 + set _CPUTAPID 0x4ba00477 +} +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +if { [info exists BSTAPID] } { + set _BSTAPID $BSTAPID +} else { + # See STM Document RM0090 + # Section 32.6.3 + set _BSTAPID 0x06413041 +} +jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME + +# if srst is not fitted use SYSRESETREQ to +# perform a soft reset +cortex_m3 reset_config sysresetreq http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/35529b95/hw/bsp/stm32f767-nucleo/boot-stm32f767-nucleo.ld ---------------------------------------------------------------------- diff --git a/hw/bsp/stm32f767-nucleo/boot-stm32f767-nucleo.ld b/hw/bsp/stm32f767-nucleo/boot-stm32f767-nucleo.ld new file mode 100644 index 0000000..e710868 --- /dev/null +++ b/hw/bsp/stm32f767-nucleo/boot-stm32f767-nucleo.ld @@ -0,0 +1,30 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 32K + ITCM (rx) : ORIGIN = 0x00000000, LENGTH = 16K + DTCM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K + RAM (rwx) : ORIGIN = 0x20020000, LENGTH = 512K +} + +/* The bootloader does not contain an image header */ +_imghdr_size = 0x0; http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/35529b95/hw/bsp/stm32f767-nucleo/bsp.yml ---------------------------------------------------------------------- diff --git a/hw/bsp/stm32f767-nucleo/bsp.yml b/hw/bsp/stm32f767-nucleo/bsp.yml new file mode 100644 index 0000000..b0dd3dd --- /dev/null +++ b/hw/bsp/stm32f767-nucleo/bsp.yml @@ -0,0 +1,61 @@ +# +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# + +bsp.arch: cortex_m7 +bsp.compiler: compiler/arm-none-eabi-m7 +bsp.linkerscript: + - "hw/bsp/stm32f767-nucleo/stm32f767-nucleo.ld" + - "hw/mcu/stm/stm32f7xx/stm32f767.ld" +bsp.linkerscript.BOOT_LOADER.OVERWRITE: + - "hw/bsp/stm32f767-nucleo/boot-stm32f767-nucleo.ld" + - "hw/mcu/stm/stm32f7xx/stm32f767.ld" +bsp.downloadscript: "hw/bsp/stm32f767-nucleo/nucleo767_download.sh" +bsp.debugscript: "hw/bsp/stm32f767-nucleo/nucleo767_debug.sh" + +bsp.flash_map: + areas: + # System areas. + FLASH_AREA_BOOTLOADER: + device: 0 + offset: 0x08000000 + size: 32kB + FLASH_AREA_IMAGE_0: + device: 0 + offset: 0x08040000 + size: 768kB + FLASH_AREA_IMAGE_1: + device: 0 + offset: 0x08100000 + size: 768kB + FLASH_AREA_IMAGE_SCRATCH: + device: 0 + offset: 0x081c0000 + size: 256kB + + # User areas. + FLASH_AREA_REBOOT_LOG: + user_id: 0 + device: 0 + offset: 0x08008000 + size: 32kB + FLASH_AREA_NFFS: + user_id: 1 + device: 0 + offset: 0x08010000 + size: 64kB http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/35529b95/hw/bsp/stm32f767-nucleo/include/bsp/bsp.h ---------------------------------------------------------------------- diff --git a/hw/bsp/stm32f767-nucleo/include/bsp/bsp.h b/hw/bsp/stm32f767-nucleo/include/bsp/bsp.h new file mode 100644 index 0000000..f77b7ab --- /dev/null +++ b/hw/bsp/stm32f767-nucleo/include/bsp/bsp.h @@ -0,0 +1,61 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ +#ifndef H_BSP_H +#define H_BSP_H + +#include <inttypes.h> +#include <mcu/mcu.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Define special stackos sections */ +#define sec_data_core __attribute__((section(".data.core"))) +#define sec_bss_core __attribute__((section(".bss.core"))) +#define sec_bss_nz_core __attribute__((section(".bss.core.nz"))) + +/* More convenient section placement macros. */ +#define bssnz_t sec_bss_nz_core + +extern uint8_t _ram_start; +extern uint8_t _dtcmram_start; +extern uint8_t _itcmram_start; +extern uint8_t _ram2_start; + +#define RAM_SIZE (368 * 1024) +#define RAM2_SIZE (16 * 1024) +#define DTCMRAM_SIZE (128 * 1024) +#define ITCMRAM_SIZE (16 * 1024) + +/* LED pins */ +#define LED_BLINK_PIN MCU_GPIO_PORTB(0) +#define LED_2 MCU_GPIO_PORTB(7) + +/* UART */ +#define UART_CNT 1 +#define CONSOLE_UART "uart0" + +#define NFFS_AREA_MAX (8) + +#ifdef __cplusplus +} +#endif + +#endif /* H_BSP_H */ http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/35529b95/hw/bsp/stm32f767-nucleo/include/bsp/cmsis_nvic.h ---------------------------------------------------------------------- diff --git a/hw/bsp/stm32f767-nucleo/include/bsp/cmsis_nvic.h b/hw/bsp/stm32f767-nucleo/include/bsp/cmsis_nvic.h new file mode 100644 index 0000000..5558988 --- /dev/null +++ b/hw/bsp/stm32f767-nucleo/include/bsp/cmsis_nvic.h @@ -0,0 +1,29 @@ +/* mbed Microcontroller Library - cmsis_nvic + * Copyright (c) 2009-2011 ARM Limited. All rights reserved. + * + * CMSIS-style functionality to support dynamic vectors + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#include <stdint.h> + +#define NVIC_NUM_VECTORS (16 + 109) // CORE + MCU Peripherals +#define NVIC_USER_IRQ_OFFSET 16 + +#include "stm32f7xx.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_Relocate(void); +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/35529b95/hw/bsp/stm32f767-nucleo/include/bsp/stm32f7xx_hal_conf.h ---------------------------------------------------------------------- diff --git a/hw/bsp/stm32f767-nucleo/include/bsp/stm32f7xx_hal_conf.h b/hw/bsp/stm32f767-nucleo/include/bsp/stm32f7xx_hal_conf.h new file mode 100644 index 0000000..7804762 --- /dev/null +++ b/hw/bsp/stm32f767-nucleo/include/bsp/stm32f7xx_hal_conf.h @@ -0,0 +1,446 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_conf.h + * @author MCD Application Team + * @version V1.0.1 + * @date 30-December-2016 + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_CONF_H +#define __STM32F7xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +#define HAL_ADC_MODULE_ENABLED +#define HAL_CAN_MODULE_ENABLED +#define HAL_CEC_MODULE_ENABLED +#define HAL_CRC_MODULE_ENABLED +/*#define HAL_CRYP_MODULE_ENABLED*/ +#define HAL_DAC_MODULE_ENABLED +#define HAL_DCMI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_DMA2D_MODULE_ENABLED +#define HAL_ETH_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_NAND_MODULE_ENABLED +#define HAL_NOR_MODULE_ENABLED +#define HAL_SRAM_MODULE_ENABLED +#define HAL_SDRAM_MODULE_ENABLED +/*#define HAL_HASH_MODULE_ENABLED*/ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_I2S_MODULE_ENABLED +#define HAL_IWDG_MODULE_ENABLED +#define HAL_LPTIM_MODULE_ENABLED +#define HAL_LTDC_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_QSPI_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_RNG_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED +#define HAL_SAI_MODULE_ENABLED +#define HAL_SD_MODULE_ENABLED +#define HAL_SPDIFRX_MODULE_ENABLED +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIM_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +#define HAL_USART_MODULE_ENABLED +#define HAL_IRDA_MODULE_ENABLED +#define HAL_SMARTCARD_MODULE_ENABLED +#define HAL_WWDG_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_PCD_MODULE_ENABLED +#define HAL_HCD_MODULE_ENABLED +#define HAL_DFSDM_MODULE_ENABLED +/* #define HAL_DSI_MODULE_ENABLED */ +#define HAL_JPEG_MODULE_ENABLED +#define HAL_MDIOS_MODULE_ENABLED + + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0x0FU) /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U +#define ART_ACCLERATOR_ENABLE 1U /* To enable instruction cache and prefetch */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1 */ + +/* ################## Ethernet peripheral configuration for NUCLEO 144 board ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2U +#define MAC_ADDR1 0U +#define MAC_ADDR2 0U +#define MAC_ADDR3 0U +#define MAC_ADDR4 0U +#define MAC_ADDR5 0U + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB ((uint32_t)5) /* 5 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((uint32_t)5) /* 5 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ +/* LAN8742A PHY Address*/ +#define LAN8742A_PHY_ADDRESS 0x00 +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY ((uint32_t)0x00000FFF) +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF) + +#define PHY_READ_TO ((uint32_t)0x0000FFFF) +#define PHY_WRITE_TO ((uint32_t)0x0000FFFF) + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ + +#define PHY_SR ((uint16_t)0x1F) /*!< PHY special control/ status register Offset */ + +#define PHY_SPEED_STATUS ((uint16_t)0x0004) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0010) /*!< PHY Duplex mask */ + + +#define PHY_ISFR ((uint16_t)0x1D) /*!< PHY Interrupt Source Flag register Offset */ +#define PHY_ISFR_INT4 ((uint16_t)0x0010) /*!< PHY Link down inturrupt */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 1U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f7xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f7xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f7xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f7xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f7xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f7xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f7xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f7xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f7xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f7xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f7xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f7xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f7xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f7xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f7xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f7xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f7xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f7xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f7xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f7xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f7xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f7xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f7xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f7xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f7xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f7xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f7xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f7xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f7xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f7xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32f7xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f7xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f7xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f7xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f7xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f7xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f7xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f7xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f7xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f7xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32f7xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32f7xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_JPEG_MODULE_ENABLED + #include "stm32f7xx_hal_jpeg.h" +#endif /* HAL_JPEG_MODULE_ENABLED */ + +#ifdef HAL_MDIOS_MODULE_ENABLED + #include "stm32f7xx_hal_mdios.h" +#endif /* HAL_MDIOS_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_CONF_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/35529b95/hw/bsp/stm32f767-nucleo/nucleo767.cfg ---------------------------------------------------------------------- diff --git a/hw/bsp/stm32f767-nucleo/nucleo767.cfg b/hw/bsp/stm32f767-nucleo/nucleo767.cfg new file mode 100644 index 0000000..4ce46f0 --- /dev/null +++ b/hw/bsp/stm32f767-nucleo/nucleo767.cfg @@ -0,0 +1,22 @@ +#!/bin/sh +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. + +# New version of St-link +source [find interface/stlink-v2-1.cfg] +transport select hla_swd +source [find target/stm32f7x.cfg] http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/35529b95/hw/bsp/stm32f767-nucleo/nucleo767_debug.sh ---------------------------------------------------------------------- diff --git a/hw/bsp/stm32f767-nucleo/nucleo767_debug.sh b/hw/bsp/stm32f767-nucleo/nucleo767_debug.sh new file mode 100755 index 0000000..5e548be --- /dev/null +++ b/hw/bsp/stm32f767-nucleo/nucleo767_debug.sh @@ -0,0 +1,37 @@ +#!/bin/sh +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# + +# Called with following variables set: +# - CORE_PATH is absolute path to @apache-mynewt-core +# - BSP_PATH is absolute path to hw/bsp/bsp_name +# - BIN_BASENAME is the path to prefix to target binary, +# .elf appended to name is the ELF file +# - FEATURES holds the target features string +# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software +# - RESET set if target should be reset when attaching +# - NO_GDB set if we should not start gdb to debug +# +. $CORE_PATH/hw/scripts/openocd.sh + +FILE_NAME=$BIN_BASENAME.elf +CFG="-s $BSP_PATH -f $BSP_PATH/nucleo767.cfg" +# Exit openocd when gdb detaches. +EXTRA_JTAG_CMD="$EXTRA_JTAG_CMD; stm32f7x.cpu configure -event gdb-detach {if {[stm32f7x.cpu curstate] eq \"halted\"} resume;shutdown}" + +openocd_debug http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/35529b95/hw/bsp/stm32f767-nucleo/nucleo767_download.sh ---------------------------------------------------------------------- diff --git a/hw/bsp/stm32f767-nucleo/nucleo767_download.sh b/hw/bsp/stm32f767-nucleo/nucleo767_download.sh new file mode 100755 index 0000000..74532fb --- /dev/null +++ b/hw/bsp/stm32f767-nucleo/nucleo767_download.sh @@ -0,0 +1,41 @@ +#!/bin/sh +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# + +# Called with following variables set: +# - CORE_PATH is absolute path to @apache-mynewt-core +# - BSP_PATH is absolute path to hw/bsp/bsp_name +# - BIN_BASENAME is the path to prefix to target binary, +# .elf appended to name is the ELF file +# - IMAGE_SLOT is the image slot to download to (for non-mfg-image, non-boot) +# - FEATURES holds the target features string +# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software +# - MFG_IMAGE is "1" if this is a manufacturing image +# - FLASH_OFFSET contains the flash offset to download to +# - BOOT_LOADER is set if downloading a bootloader +. $CORE_PATH/hw/scripts/openocd.sh + +CFG="-s $BSP_PATH -f nucleo767.cfg" + +if [ "$MFG_IMAGE" ]; then + FLASH_OFFSET=0x08000000 +fi + +common_file_to_load +openocd_load +openocd_reset_run http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/35529b95/hw/bsp/stm32f767-nucleo/pkg.yml ---------------------------------------------------------------------- diff --git a/hw/bsp/stm32f767-nucleo/pkg.yml b/hw/bsp/stm32f767-nucleo/pkg.yml new file mode 100644 index 0000000..5b3e684 --- /dev/null +++ b/hw/bsp/stm32f767-nucleo/pkg.yml @@ -0,0 +1,40 @@ +# +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# + +pkg.name: hw/bsp/stm32f767-nucleo +pkg.type: bsp +pkg.description: BSP definition for the stm32f767-nucleo board. +pkg.author: "Apache Mynewt <d...@mynewt.incubator.apache.org>" +pkg.homepage: "http://mynewt.apache.org/" +pkg.keywords: + - stm32 + - stm32f7 + - nucleo + +pkg.cflags: -DSTM32F767xx + +pkg.cflags.HARDFLOAT: + - -mfloat-abi=hard -mfpu=fpv4-sp-d16 + +pkg.deps: + - hw/mcu/stm/stm32f7xx + - libc/baselibc + +pkg.deps.UART_0: + - hw/drivers/uart/uart_hal http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/35529b95/hw/bsp/stm32f767-nucleo/src/arch/cortex_m7/startup_stm32f767xx.s ---------------------------------------------------------------------- diff --git a/hw/bsp/stm32f767-nucleo/src/arch/cortex_m7/startup_stm32f767xx.s b/hw/bsp/stm32f767-nucleo/src/arch/cortex_m7/startup_stm32f767xx.s new file mode 100644 index 0000000..eddc2c2 --- /dev/null +++ b/hw/bsp/stm32f767-nucleo/src/arch/cortex_m7/startup_stm32f767xx.s @@ -0,0 +1,652 @@ +/** + ****************************************************************************** + * @file startup_stm32f767xx.s + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief STM32F767xx Devices vector table for GCC based toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M7 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m7 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + + ldr r2, =_sbss + b LoopFillZerobss + +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* + * mynewt specific corebss clearing. + */ + ldr r2, =__corebss_start__ + b LoopFillZeroCoreBss + +/* Zero fill the bss segment. */ +FillZeroCoreBss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZeroCoreBss: + ldr r3, =__corebss_end__ + cmp r2, r3 + bcc FillZeroCoreBss + +/* Call the clock system initialization function.*/ + bl SystemInit +/* Call the libc entry point.*/ + bl _start +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M7. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .globl __isr_vector +__isr_vector: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FMC_IRQHandler /* FMC */ + .word SDMMC1_IRQHandler /* SDMMC1 */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word 0 /* Reserved */ + .word RNG_IRQHandler /* RNG */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word SAI1_IRQHandler /* SAI1 */ + .word LTDC_IRQHandler /* LTDC */ + .word LTDC_ER_IRQHandler /* LTDC error */ + .word DMA2D_IRQHandler /* DMA2D */ + .word SAI2_IRQHandler /* SAI2 */ + .word QUADSPI_IRQHandler /* QUADSPI */ + .word LPTIM1_IRQHandler /* LPTIM1 */ + .word CEC_IRQHandler /* HDMI_CEC */ + .word I2C4_EV_IRQHandler /* I2C4 Event */ + .word I2C4_ER_IRQHandler /* I2C4 Error */ + .word SPDIF_RX_IRQHandler /* SPDIF_RX */ + .word 0 /* Reserved */ + .word DFSDM1_FLT0_IRQHandler /* DFSDM1 Filter 0 global Interrupt */ + .word DFSDM1_FLT1_IRQHandler /* DFSDM1 Filter 1 global Interrupt */ + .word DFSDM1_FLT2_IRQHandler /* DFSDM1 Filter 2 global Interrupt */ + .word DFSDM1_FLT3_IRQHandler /* DFSDM1 Filter 3 global Interrupt */ + .word SDMMC2_IRQHandler /* SDMMC2 */ + .word CAN3_TX_IRQHandler /* CAN3 TX */ + .word CAN3_RX0_IRQHandler /* CAN3 RX0 */ + .word CAN3_RX1_IRQHandler /* CAN3 RX1 */ + .word CAN3_SCE_IRQHandler /* CAN3 SCE */ + .word JPEG_IRQHandler /* JPEG */ + .word MDIOS_IRQHandler /* MDIOS */ + .size __isr_vector, . - __isr_vector + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak LTDC_IRQHandler + .thumb_set LTDC_IRQHandler,Default_Handler + + .weak LTDC_ER_IRQHandler + .thumb_set LTDC_ER_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + + .weak SAI2_IRQHandler + .thumb_set SAI2_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak SPDIF_RX_IRQHandler + .thumb_set SPDIF_RX_IRQHandler,Default_Handler + + .weak DFSDM1_FLT0_IRQHandler + .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler + + .weak DFSDM1_FLT1_IRQHandler + .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler + + .weak DFSDM1_FLT2_IRQHandler + .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler + + .weak DFSDM1_FLT3_IRQHandler + .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler + + .weak SDMMC2_IRQHandler + .thumb_set SDMMC2_IRQHandler,Default_Handler + + .weak CAN3_TX_IRQHandler + .thumb_set CAN3_TX_IRQHandler,Default_Handler + + .weak CAN3_RX0_IRQHandler + .thumb_set CAN3_RX0_IRQHandler,Default_Handler + + .weak CAN3_RX1_IRQHandler + .thumb_set CAN3_RX1_IRQHandler,Default_Handler + + .weak CAN3_SCE_IRQHandler + .thumb_set CAN3_SCE_IRQHandler,Default_Handler + + .weak JPEG_IRQHandler + .thumb_set JPEG_IRQHandler,Default_Handler + + .weak MDIOS_IRQHandler + .thumb_set MDIOS_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/35529b95/hw/bsp/stm32f767-nucleo/src/hal_bsp.c ---------------------------------------------------------------------- diff --git a/hw/bsp/stm32f767-nucleo/src/hal_bsp.c b/hw/bsp/stm32f767-nucleo/src/hal_bsp.c new file mode 100644 index 0000000..34fd01c --- /dev/null +++ b/hw/bsp/stm32f767-nucleo/src/hal_bsp.c @@ -0,0 +1,133 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ +#include <assert.h> + +#include <syscfg/syscfg.h> + +#include <os/os_dev.h> +#if MYNEWT_VAL(UART_0) +#include <uart/uart.h> +#include <uart_hal/uart_hal.h> +#endif + +#include <hal/hal_bsp.h> +#include <hal/hal_gpio.h> +#include <hal/hal_flash_int.h> +#include <hal/hal_timer.h> + +#include <stm32f767xx.h> +#include <stm32f7xx_hal_gpio_ex.h> +#include <mcu/stm32f7_bsp.h> + +#include "bsp/bsp.h" + +#if MYNEWT_VAL(UART_0) +static struct uart_dev hal_uart0; + +static const struct stm32f7_uart_cfg uart_cfg[UART_CNT] = { + [0] = { + .suc_uart = USART3, + .suc_rcc_reg = &RCC->APB1ENR, + .suc_rcc_dev = RCC_APB1ENR_USART3EN, + .suc_pin_tx = MCU_GPIO_PORTD(8), /* PD8 */ + .suc_pin_rx = MCU_GPIO_PORTD(9), /* PD9 */ + .suc_pin_rts = -1, + .suc_pin_cts = -1, + .suc_pin_af = GPIO_AF7_USART3, + .suc_irqn = USART3_IRQn, + } +}; +#endif + +/* FIXME */ +static const struct hal_bsp_mem_dump dump_cfg[] = { + [0] = { + .hbmd_start = &_ram_start, + .hbmd_size = RAM_SIZE, + }, + [1] = { + .hbmd_start = &_dtcmram_start, + .hbmd_size = DTCMRAM_SIZE, + }, + [2] = { + .hbmd_start = &_itcmram_start, + .hbmd_size = ITCMRAM_SIZE, + }, +}; + +const struct hal_flash * +hal_bsp_flash_dev(uint8_t id) +{ + /* + * Internal flash mapped to id 0. + */ + if (id != 0) { + return NULL; + } + return &stm32f7_flash_dev; +} + +const struct hal_bsp_mem_dump * +hal_bsp_core_dump(int *area_cnt) +{ + *area_cnt = sizeof(dump_cfg) / sizeof(dump_cfg[0]); + return dump_cfg; +} + +void +hal_bsp_init(void) +{ + int rc; + + (void)rc; + +#if MYNEWT_VAL(UART_0) + rc = os_dev_create((struct os_dev *) &hal_uart0, CONSOLE_UART, + OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)&uart_cfg[0]); + assert(rc == 0); +#endif + +#if MYNEWT_VAL(TIMER_0) + hal_timer_init(0, TIM1); +#endif + +#if MYNEWT_VAL(TIMER_1) + hal_timer_init(1, TIM8); +#endif + +#if MYNEWT_VAL(TIMER_2) + hal_timer_init(2, TIM9); +#endif +} + +/** + * Returns the configured priority for the given interrupt. If no priority + * configured, return the priority passed in + * + * @param irq_num + * @param pri + * + * @return uint32_t + */ +uint32_t +hal_bsp_get_nvic_priority(int irq_num, uint32_t pri) +{ + /* Add any interrupt priorities configured by the bsp here */ + return pri; +} http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/35529b95/hw/bsp/stm32f767-nucleo/src/sbrk.c ---------------------------------------------------------------------- diff --git a/hw/bsp/stm32f767-nucleo/src/sbrk.c b/hw/bsp/stm32f767-nucleo/src/sbrk.c new file mode 100644 index 0000000..34edf72 --- /dev/null +++ b/hw/bsp/stm32f767-nucleo/src/sbrk.c @@ -0,0 +1,50 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +extern char __HeapBase; +extern char __HeapLimit; + +void * +_sbrk(int incr) +{ + static char *brk = &__HeapBase; + + void *prev_brk; + + if (incr < 0) { + /* Returning memory to the heap. */ + incr = -incr; + if (brk - incr < &__HeapBase) { + prev_brk = (void *)-1; + } else { + prev_brk = brk; + brk -= incr; + } + } else { + /* Allocating memory from the heap. */ + if (&__HeapLimit - brk >= incr) { + prev_brk = brk; + brk += incr; + } else { + prev_brk = (void *)-1; + } + } + + return prev_brk; +}