raiden00pl commented on code in PR #16500: URL: https://github.com/apache/nuttx/pull/16500#discussion_r2144748013
########## arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h: ########## @@ -108,9 +113,16 @@ #define STM32_ADC1_CFGR2 (STM32_ADC1_BASE + STM32_ADC_CFGR2_OFFSET) #define STM32_ADC1_SMPR (STM32_ADC1_BASE + STM32_ADC_SMPR_OFFSET) #define STM32_ADC1_TR (STM32_ADC1_BASE + STM32_ADC_TR_OFFSET) +#define STM32_ADC1_AWD2TR (STM32_ADC1_BASE + STM32_ADC_AWD2TR_OFFSET) #define STM32_ADC1_CHSELR (STM32_ADC1_BASE + STM32_ADC_CHSELR_OFFSET) +#define STM32_ADC1_AWD3TR (STM32_ADC1_BASE + STM32_ADC_AWD3TR_OFFSET) #define STM32_ADC1_DR (STM32_ADC1_BASE + STM32_ADC_DR_OFFSET) -#define STM32_ADC1_CCR (STM32_ADC1_BASE + STM32_ADC_CCR_OFFSET) +#define STM32_ADC1_AWD2CR (STM32_ADC1_BASE + STM32_ADC_AWD2CR_OFFSET) +#define STM32_ADC1_AWD3CR (STM32_ADC1_BASE + STM32_ADC_AWD3CR_OFFSET) +#define STM32_ADC1_CALFACT (STM32_ADC1_BASE + STM32_ADC_CALFACT_OFFSET) +#if defined(CONFIG_ARCH_CHIP_STM32G0) +# define STM32_ADC1_CCR (STM32_ADC1_BASE + STM32_ADC_CCR_OFFSET) Review Comment: STM32_ADC1_CCR points to the wrong address, it's better to remove it -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: commits-unsubscr...@nuttx.apache.org For queries about this service, please contact Infrastructure at: us...@infra.apache.org
