kywwilson11 opened a new pull request, #17007:
URL: https://github.com/apache/nuttx/pull/17007
## Summary
I added analog watchdog 1 (AWD1) support to the STM32H5 lower-half ADC
driver and introduced a per-channel configuration structure so we can describe
each configured channel explicitly. That lets us (a) select single-ended vs
differential channels, (b) apply sample times per channel, and (c) defined as a
regular or injected channel (future add). I also wired up Kconfig to make AWD1
initialization selectable per ADC instance.
On the driver side:
- Implement AWD1 init/enable paths and hook them into the ISR. The ISR does
**not** stop conversions when the window trips; it disables the AWD1 interrupt.
Users can re-enable it via the existing IOCTL flow (details below).
- Cleaned up and hardened the existing IOCTLs for upper/lower threshold
configuration so they behave consistently (and safely) with conversions running.
- Added a `adc_reset_dma()` helper to realign circular DMA after stopping
conversions; otherwise the DMA buffer and conversion stream can drift.
On the platform side:
- Switched the H563ZI pin map to `INP*/INN*` naming so differential pairs
are first-class, and provided a simple example board setup using channels 3 and
10 with per-channel sample times.
New/updated Kconfig (per-ADC):
- `STM32H5_ADC{1,2}_WDG1` to enable AWD1 at init
- Filter and threshold knobs: `STM32H5_ADC{1,2}_WDG1_FLT`, `_LOWTHRESH`,
`_HIGHTHRESH`
- Scope selection: `STM32H5_ADC{1,2}_WDG1_SGL` (single channel) +
`STM32H5_ADC{1,2}_WDG1_CHAN` (which channel)
## Impact
**Users / behavior**
- Normal ADC conversions are unaffected.
- When AWD1 is enabled, an out-of-window event disables **only** the AWD1
interrupt; conversions keep running. Re-enable via the watchdog IOCTL after
handling the event.
- Per-channel config enables mixed sampling times and differential mode
selection (per channel) without touching global defaults.
**Build / configuration**
- New Kconfig options are default-off, so no change unless explicitly
enabled.
- Boards that referenced legacy `GPIO_ADCx_IN*` names should migrate to the
new `GPIO_ADCx_INP*/INN*` macros.
**API / driver interfaces**
- Threshold IOCTLs are retained but made more robust; naming is aligned with
the STM32H5 ADC set.
- Added an internal `adc_reset_dma()` path to safely recover circular DMA
state after a stop.
**Docs / compatibility / security**
- No security impact.
- Backward compatible for existing single-ended setups; differential support
and AWD1 are opt-in.
- It would be good to add a short note in the STM32H5 ADC docs about the
AWD1 Kconfig and the per-channel struct.
## Testing
**Host / toolchain**
- x86_64 Linux host; standard NuttX stm32h5 toolchain. (I’ll attach exact
toolchain version and logs in a follow-up.)
**Board**
- NUCLEO-H563ZI
**Config**
- ADC1 enabled with two channels configured via the per-channel array:
- CH3 and CH10, both single-ended, `tsamp = ADC_SMPR_640p5`
- AWD1 enabled for ADC1 with:
- `low = 0`, `high = 2048`
- Tested in both “all channels” mode and “single channel” mode (selected
channel varied between 3 and 10)
**Procedure**
1. Build and flash NuttX with the above Kconfig. Register `/dev/adc0` via
the board init.
2. Start continuous conversions (DMA circular enabled) and run the `adc`
example to sanity-check normal operation.
3. Tie both CH3 and CH10 to GND → verified **no** AWD interrupts and ADC
continues normally.
4. Tie either CH3 or CH10 to 3.3 V with AWD1 set to “all channels” → ISR
fires as expected; conversions continue; AWD1 IRQ is disabled by the ISR.
5. Switch to single-channel AWD1:
- Select CH3: drive CH3 above the window → ISR fires; drive CH10 above
the window → **no** ISR.
- Select CH10: mirror the above.
6. Re-enable the watchdog interrupt using the driver IOCTL; confirm
subsequent out-of-window events retrigger the ISR.
7. DMA circular mode check: stop conversions, call the DMA reset helper,
restart conversions → verify buffer alignment and sample sequence remain
correct.
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