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xiaoxiang pushed a commit to branch master
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The following commit(s) were added to refs/heads/master by this push:
new ec04ef9ccfd arch/arm/xmc4 : various fixes and clean - Fix EtherCAT
signals drive strengh (from errata PORTS_CM.H002), caused bus faults. - Changed
xmc4_ecat.c for compile time pin definition. - Fixed xmc4_ecat.c register not
written (reset value already used). - Removed EXTCLK for xmc4800 as pin is used
for ECAT. - Clean xmc4 familly board.h and clocks config.
ec04ef9ccfd is described below
commit ec04ef9ccfd1998896509c3231e4f7e7b40508b7
Author: adriendesp <[email protected]>
AuthorDate: Tue Dec 2 10:20:17 2025 +0100
arch/arm/xmc4 : various fixes and clean
- Fix EtherCAT signals drive strengh (from errata PORTS_CM.H002), caused
bus faults.
- Changed xmc4_ecat.c for compile time pin definition.
- Fixed xmc4_ecat.c register not written (reset value already used).
- Removed EXTCLK for xmc4800 as pin is used for ECAT.
- Clean xmc4 familly board.h and clocks config.
Signed-off-by: adriendesp <[email protected]>
---
arch/arm/src/xmc4/hardware/xmc4_pinmux.h | 40 +-
arch/arm/src/xmc4/hardware/xmc4_scu.h | 8 +-
arch/arm/src/xmc4/xmc4_clockconfig.c | 6 +-
arch/arm/src/xmc4/xmc4_ecat.c | 870 +++++++++-----------------
arch/arm/src/xmc4/xmc4_gpio.h | 2 +-
boards/arm/xmc4/xmc4500-relax/include/board.h | 27 +-
boards/arm/xmc4/xmc4700-relax/include/board.h | 32 +-
boards/arm/xmc4/xmc4800-relax/include/board.h | 53 +-
8 files changed, 387 insertions(+), 651 deletions(-)
diff --git a/arch/arm/src/xmc4/hardware/xmc4_pinmux.h
b/arch/arm/src/xmc4/hardware/xmc4_pinmux.h
index 69deccaf5c1..f5f084f2b5d 100644
--- a/arch/arm/src/xmc4/hardware/xmc4_pinmux.h
+++ b/arch/arm/src/xmc4/hardware/xmc4_pinmux.h
@@ -376,13 +376,13 @@
#define GPIO_EBU_SDCLKO_2 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT6
| GPIO_PIN4)
#define GPIO_EBU_WAIT (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT3 |
GPIO_PIN3)
-#define GPIO_ECAT_CONF_OUTPUT GPIO_OUTPUT | GPIO_OUTPUT_PUSHPULL |
GPIO_PINCTRL_SOFTWARE | GPIO_OUTPUT_CLEAR
-#define GPIO_ECAT_CLK_25_1 (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSHARP | GPIO_PORT6 | GPIO_PIN0 | GPIO_OUTPUT_ALT4)
-#define GPIO_ECAT_CLK_25_2 (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSHARP | GPIO_PORT1 | GPIO_PIN13 | GPIO_OUTPUT_ALT4)
+#define GPIO_ECAT_CONF_OUTPUT (GPIO_OUTPUT | GPIO_OUTPUT_PUSHPULL |
GPIO_PINCTRL_SOFTWARE | GPIO_OUTPUT_CLEAR)
+#define GPIO_ECAT_CLK_25_1 (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSOFT | GPIO_PORT6 | GPIO_PIN0 | GPIO_OUTPUT_ALT4)
+#define GPIO_ECAT_CLK_25_2 (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSOFT | GPIO_PORT1 | GPIO_PIN13 | GPIO_OUTPUT_ALT4)
#define GPIO_ECAT_LED_RUN (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSOFT | GPIO_PORT0 | GPIO_PIN8 | GPIO_OUTPUT_ALT3)
#define GPIO_ECAT_LED_ERR (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSOFT | GPIO_PORT0 | GPIO_PIN7 | GPIO_OUTPUT_ALT3)
-#define GPIO_ECAT_MCLK (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSHARP | GPIO_PORT3 | GPIO_PIN3 | GPIO_OUTPUT_ALT4)
-#define GPIO_ECAT_MDO (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN12)
+#define GPIO_ECAT_MCLK (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSOFT | GPIO_PORT3 | GPIO_PIN3 | GPIO_OUTPUT_ALT4)
+#define GPIO_ECAT_MDO (GPIO_INPUT | GPIO_PINCTRL_HW1 |
GPIO_PORT0 | GPIO_PIN12)
#define GPIO_ECAT_P0_LED_LINK_ACT_1 (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSOFT | GPIO_PORT6 | GPIO_PIN3 | GPIO_OUTPUT_ALT4)
#define GPIO_ECAT_P0_LED_LINK_ACT_2 (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSOFT | GPIO_PORT1 | GPIO_PIN12 | GPIO_OUTPUT_ALT4)
#define GPIO_ECAT_P0_LINK_STATUS (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN15)
@@ -401,16 +401,16 @@
#define GPIO_ECAT_P0_RX_ERR (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN6)
#define GPIO_ECAT_P0_TX_CLK_1 (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN5)
#define GPIO_ECAT_P0_TX_CLK_2 (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN0)
-#define GPIO_ECAT_P0_TXD0_1 (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSHARP | GPIO_PORT6 | GPIO_PIN2 | GPIO_OUTPUT_ALT4)
-#define GPIO_ECAT_P0_TXD0_2 (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSHARP | GPIO_PORT1 | GPIO_PIN6 | GPIO_OUTPUT_ALT1)
-#define GPIO_ECAT_P0_TXD1_1 (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSHARP | GPIO_PORT6 | GPIO_PIN4 | GPIO_OUTPUT_ALT4)
-#define GPIO_ECAT_P0_TXD1_2 (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSHARP | GPIO_PORT1 | GPIO_PIN7 | GPIO_OUTPUT_ALT1)
-#define GPIO_ECAT_P0_TXD2_1 (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSHARP | GPIO_PORT6 | GPIO_PIN5 | GPIO_OUTPUT_ALT4)
-#define GPIO_ECAT_P0_TXD2_2 (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSHARP | GPIO_PORT1 | GPIO_PIN8 | GPIO_OUTPUT_ALT1)
-#define GPIO_ECAT_P0_TXD3_1 (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSHARP | GPIO_PORT6 | GPIO_PIN6 | GPIO_OUTPUT_ALT4)
-#define GPIO_ECAT_P0_TXD3_2 (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSHARP | GPIO_PORT1 | GPIO_PIN2 | GPIO_OUTPUT_ALT1)
-#define GPIO_ECAT_P0_TX_EN_1 (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSHARP | GPIO_PORT6 | GPIO_PIN1 | GPIO_OUTPUT_ALT4)
-#define GPIO_ECAT_P0_TX_EN_2 (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSHARP | GPIO_PORT1 | GPIO_PIN3 | GPIO_OUTPUT_ALT1)
+#define GPIO_ECAT_P0_TXD0_1 (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSOFT | GPIO_PORT6 | GPIO_PIN2 | GPIO_OUTPUT_ALT4)
+#define GPIO_ECAT_P0_TXD0_2 (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSOFT | GPIO_PORT1 | GPIO_PIN6 | GPIO_OUTPUT_ALT1)
+#define GPIO_ECAT_P0_TXD1_1 (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSOFT | GPIO_PORT6 | GPIO_PIN4 | GPIO_OUTPUT_ALT4)
+#define GPIO_ECAT_P0_TXD1_2 (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSOFT | GPIO_PORT1 | GPIO_PIN7 | GPIO_OUTPUT_ALT1)
+#define GPIO_ECAT_P0_TXD2_1 (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSOFT | GPIO_PORT6 | GPIO_PIN5 | GPIO_OUTPUT_ALT4)
+#define GPIO_ECAT_P0_TXD2_2 (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSOFT | GPIO_PORT1 | GPIO_PIN8 | GPIO_OUTPUT_ALT1)
+#define GPIO_ECAT_P0_TXD3_1 (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSOFT | GPIO_PORT6 | GPIO_PIN6 | GPIO_OUTPUT_ALT4)
+#define GPIO_ECAT_P0_TXD3_2 (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSOFT | GPIO_PORT1 | GPIO_PIN2 | GPIO_OUTPUT_ALT1)
+#define GPIO_ECAT_P0_TX_EN_1 (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSOFT | GPIO_PORT6 | GPIO_PIN1 | GPIO_OUTPUT_ALT4)
+#define GPIO_ECAT_P0_TX_EN_2 (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSOFT | GPIO_PORT1 | GPIO_PIN3 | GPIO_OUTPUT_ALT1)
#define GPIO_ECAT_P1_LED_LINK_ACT_1 (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSOFT | GPIO_PORT3 | GPIO_PIN12 | GPIO_OUTPUT_ALT1)
#define GPIO_ECAT_P1_LED_LINK_ACT_2 (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSOFT | GPIO_PORT0 | GPIO_PIN11 | GPIO_OUTPUT_ALT1)
#define GPIO_ECAT_P1_LINK_STATUS_1 (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN4)
@@ -430,11 +430,11 @@
#define GPIO_ECAT_P1_RX_ERR_1 (GPIO_INPUT | GPIO_PORT15 | GPIO_PIN2)
#define GPIO_ECAT_P1_RX_ERR_2 (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN5)
#define GPIO_ECAT_P1_TX_CLK (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN10)
-#define GPIO_ECAT_P1_TXD0 (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSHARP | GPIO_PORT3 | GPIO_PIN1 | GPIO_OUTPUT_ALT3)
-#define GPIO_ECAT_P1_TXD1 (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSHARP | GPIO_PORT3 | GPIO_PIN2 | GPIO_OUTPUT_ALT3)
-#define GPIO_ECAT_P1_TXD2 (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSHARP | GPIO_PORT0 | GPIO_PIN2 | GPIO_OUTPUT_ALT1)
-#define GPIO_ECAT_P1_TXD3 (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSHARP | GPIO_PORT0 | GPIO_PIN3 | GPIO_OUTPUT_ALT1)
-#define GPIO_ECAT_P1_TX_EN (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSHARP | GPIO_PORT3 | GPIO_PIN0 | GPIO_OUTPUT_ALT4)
+#define GPIO_ECAT_P1_TXD0 (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSOFT | GPIO_PORT3 | GPIO_PIN1 | GPIO_OUTPUT_ALT3)
+#define GPIO_ECAT_P1_TXD1 (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSOFT | GPIO_PORT3 | GPIO_PIN2 | GPIO_OUTPUT_ALT3)
+#define GPIO_ECAT_P1_TXD2 (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSOFT | GPIO_PORT0 | GPIO_PIN2 | GPIO_OUTPUT_ALT1)
+#define GPIO_ECAT_P1_TXD3 (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSOFT | GPIO_PORT0 | GPIO_PIN3 | GPIO_OUTPUT_ALT1)
+#define GPIO_ECAT_P1_TX_EN (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSOFT | GPIO_PORT3 | GPIO_PIN0 | GPIO_OUTPUT_ALT4)
#define GPIO_ECAT_PHY_RESET (GPIO_ECAT_CONF_OUTPUT |
GPIO_PADA2_STRONGSOFT | GPIO_PORT0 | GPIO_PIN0 | GPIO_OUTPUT_ALT1)
#define GPIO_ERU0_0A0 (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN1)
diff --git a/arch/arm/src/xmc4/hardware/xmc4_scu.h
b/arch/arm/src/xmc4/hardware/xmc4_scu.h
index d7464f8494b..59f5791a677 100644
--- a/arch/arm/src/xmc4/hardware/xmc4_scu.h
+++ b/arch/arm/src/xmc4/hardware/xmc4_scu.h
@@ -465,7 +465,7 @@
#define SCU_ECAT0CON_PHY_OFFSET (1 << SCU_ECAT0CON_PHY_OFFSET_SHIFT)
#define SCU_ECAT0CON_ECATRSTEN_SHIFT (0)
-#define SCU_ECAT0CON_ECATRSTEN (0 << SCU_ECAT0CON_ECATRSTEN_SHIFT)
+#define SCU_ECAT0CON_ECATRSTEN (1 << SCU_ECAT0CON_ECATRSTEN_SHIFT)
/* Port 0 */
#define SCU_ECAT0CON_RXD0_SHIFT (0)
@@ -1097,6 +1097,12 @@
#define SCU_DSLEEPCR_CCUCR (1 << 20) /* Bit 20: CCU Clock Control in
Deep Sleep Mod */
#define SCU_DSLEEPCR_WDTCR (1 << 21) /* Bit 21: WDT Clock Control in
Deep Sleep Mode */
+/* EtherCAT clocking */
+#define SCU_ECATCLKCR_ECADIV_SHIFT (0) /* Bit 0-1: EtherCAT Clock Divider
Value */
+#define SCU_ECATCLKCR_ECATSEL_SHIFT (16) /* Bit 16: EtherCAT Clock Selection
Value */
+# define SCU_ECATCLKCR_ECATSEL_FPLLUSB (0 << SCU_ECATCLKCR_ECATSEL_SHIFT)
+# define SCU_ECATCLKCR_ECATSEL_FPLL (1 << SCU_ECATCLKCR_ECATSEL_SHIFT)
+
/* Peripheral 0 Clock Gating Status, Peripheral 0 Clock Gating Set,
* Peripheral 0 Clock Gating Clear
*/
diff --git a/arch/arm/src/xmc4/xmc4_clockconfig.c
b/arch/arm/src/xmc4/xmc4_clockconfig.c
index 3ef4d1a933c..939597b34ea 100644
--- a/arch/arm/src/xmc4/xmc4_clockconfig.c
+++ b/arch/arm/src/xmc4/xmc4_clockconfig.c
@@ -414,11 +414,13 @@ void xmc4_clock_configure(void)
putreg32(USBCLKCR_VALUE | USB_DIV, XMC4_SCU_USBCLKCR);
#endif
+#if BOARD_EXTCKL_ENABLE
/* Setup EXT */
regval = (BOARD_EXT_SOURCE << SCU_EXTCLKCR_ECKSEL_SHIFT);
regval |= SCU_EXTCLKCR_ECKDIV(BOARD_PLL_ECKDIV);
putreg32(regval, XMC4_SCU_EXTCLKCR);
+#endif
#if BOARD_ENABLE_PLL
/* PLL frequency stepping... */
@@ -528,8 +530,8 @@ void xmc4_clock_configure(void)
/* Setup Divider settings for USB PLL */
- regval = (SCU_USBPLLCON_NDIV(BOARD_USB_NDIV) |
- SCU_USBPLLCON_PDIV(BOARD_USB_PDIV));
+ regval = (SCU_USBPLLCON_NDIV(BOARD_USBPLL_NDIV) |
+ SCU_USBPLLCON_PDIV(BOARD_USBPLL_PDIV));
putreg32(regval, XMC4_SCU_USBPLLCON);
/* Set OSCDISCDIS */
diff --git a/arch/arm/src/xmc4/xmc4_ecat.c b/arch/arm/src/xmc4/xmc4_ecat.c
index 876a681b6e1..6767a390d1c 100644
--- a/arch/arm/src/xmc4/xmc4_ecat.c
+++ b/arch/arm/src/xmc4/xmc4_ecat.c
@@ -34,6 +34,274 @@
#include "hardware/xmc4_scu.h"
#include "debug.h"
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define GET_GPIO(p) ((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK))
+
+/* MDIO configuration */
+
+#if GET_GPIO(ECAT_MDO) == (GPIO_PORT0 | GPIO_PIN12)
+ #define MDIO SCU_ECAT0CON_MDIOA
+#elif GET_GPIO(ECAT_MDO) == (GPIO_PORT4 | GPIO_PIN2)
+ #define MDIO SCU_ECAT0CON_MDIOB
+#elif GET_GPIO(ECAT_MDO) == (GPIO_PORT9 | GPIO_PIN7)
+ #define MDIO SCU_ECAT0CON_MDIOC
+#else
+ #error "EtherCAT : Unknown MDIO configuration"
+#endif
+
+#if defined(CONFIG_XMC4_ECAT_P0)
+
+/* Port 0 RX D0 */
+
+#if GET_GPIO(ECAT_P0_RXD0) == (GPIO_PORT1 | GPIO_PIN4)
+ #define P0_RXD0 SCU_ECAT0CON_PORT0_RXD0A
+#elif GET_GPIO(ECAT_P0_RXD0) == (GPIO_PORT5 | GPIO_PIN0)
+ #define P0_RXD0 SCU_ECAT0CON_PORT0_RXD0B
+#elif GET_GPIO(ECAT_P0_RXD0) == (GPIO_PORT7 | GPIO_PIN4)
+ #define P0_RXD0 SCU_ECAT0CON_PORT0_RXD0C
+#else
+ #error "EtherCAT : Unknown P0_RXD0 configuration"
+#endif
+
+/* Port 0 RX D1 */
+
+#if GET_GPIO(ECAT_P0_RXD1) == (GPIO_PORT1 | GPIO_PIN5)
+ #define P0_RXD1 SCU_ECAT0CON_PORT0_RXD1A
+#elif GET_GPIO(ECAT_P0_RXD1) == (GPIO_PORT5 | GPIO_PIN1)
+ #define P0_RXD1 SCU_ECAT0CON_PORT0_RXD1B
+#elif GET_GPIO(ECAT_P0_RXD1) == (GPIO_PORT7 | GPIO_PIN5)
+ #define P0_RXD1 SCU_ECAT0CON_PORT0_RXD1C
+#else
+ #error "EtherCAT : Unknown P0_RXD1 configuration"
+#endif
+
+/* Port 0 RX D2 */
+
+#if GET_GPIO(ECAT_P0_RXD2) == (GPIO_PORT1 | GPIO_PIN10)
+ #define P0_RXD2 SCU_ECAT0CON_PORT0_RXD2A
+#elif GET_GPIO(ECAT_P0_RXD2) == (GPIO_PORT5 | GPIO_PIN2)
+ #define P0_RXD2 SCU_ECAT0CON_PORT0_RXD2B
+#elif GET_GPIO(ECAT_P0_RXD2) == (GPIO_PORT7 | GPIO_PIN6)
+ #define P0_RXD2 SCU_ECAT0CON_PORT0_RXD2C
+#else
+ #error "EtherCAT : Unknown P0_RXD2 configuration"
+#endif
+
+/* Port 0 RX D3 */
+
+#if GET_GPIO(ECAT_P0_RXD3) == (GPIO_PORT1 | GPIO_PIN11)
+ #define P0_RXD3 SCU_ECAT0CON_PORT0_RXD3A
+#elif GET_GPIO(ECAT_P0_RXD3) == (GPIO_PORT5 | GPIO_PIN7)
+ #define P0_RXD3 SCU_ECAT0CON_PORT0_RXD3B
+#elif GET_GPIO(ECAT_P0_RXD3) == (GPIO_PORT7 | GPIO_PIN7)
+ #define P0_RXD3 SCU_ECAT0CON_PORT0_RXD3C
+#else
+ #error "EtherCAT : Unknown P0_RXD3 configuration"
+#endif
+
+/* Port 0 RX CLK */
+
+#if GET_GPIO(ECAT_P0_RX_CLK) == (GPIO_PORT1 | GPIO_PIN1)
+ #define P0_RX_CLK SCU_ECAT0CON_PORT0_RX_CLKA
+#elif GET_GPIO(ECAT_P0_RX_CLK) == (GPIO_PORT5 | GPIO_PIN4)
+ #define P0_RX_CLK SCU_ECAT0CON_PORT0_RX_CLKB
+#elif GET_GPIO(ECAT_P0_RX_CLK) == (GPIO_PORT7 | GPIO_PIN10)
+ #define P0_RX_CLK SCU_ECAT0CON_PORT0_RX_CLKC
+#else
+ #error "EtherCAT : Unknown P0_RX_CLK configuration"
+#endif
+
+/* Port 0 RX DV */
+
+#if GET_GPIO(ECAT_P0_RX_DV) == (GPIO_PORT1 | GPIO_PIN9)
+ #define P0_RX_DV SCU_ECAT0CON_PORT0_RX_DVA
+#elif GET_GPIO(ECAT_P0_RX_DV) == (GPIO_PORT5 | GPIO_PIN6)
+ #define P0_RX_DV SCU_ECAT0CON_PORT0_RX_DVB
+#elif GET_GPIO(ECAT_P0_RX_DV) == (GPIO_PORT7 | GPIO_PIN11)
+ #define P0_RX_DV SCU_ECAT0CON_PORT0_RX_DVC
+#else
+ #error "EtherCAT : Unknown P0_RX_DV configuration"
+#endif
+
+/* Port 0 RX ERR */
+
+#if GET_GPIO(ECAT_P0_RX_ERR) == (GPIO_PORT4 | GPIO_PIN0)
+ #define P0_RX_ERR SCU_ECAT0CON_PORT0_RX_ERRA
+#elif GET_GPIO(ECAT_P0_RX_ERR) == (GPIO_PORT2 | GPIO_PIN6)
+ #define P0_RX_ERR SCU_ECAT0CON_PORT0_RX_ERRB
+#elif GET_GPIO(ECAT_P0_RX_ERR) == (GPIO_PORT7 | GPIO_PIN9)
+ #define P0_RX_ERR SCU_ECAT0CON_PORT0_RX_ERRC
+#else
+ #error "EtherCAT : Unknown P0_RX_ERR configuration"
+#endif
+
+/* Port 0 LINK */
+
+#if GET_GPIO(ECAT_P0_LINK_STATUS) == (GPIO_PORT4 | GPIO_PIN1)
+ #define P0_LINK_STATUS SCU_ECAT0CON_PORT0_LINKA
+#elif GET_GPIO(ECAT_P0_LINK_STATUS) == (GPIO_PORT1 | GPIO_PIN15)
+ #define P0_LINK_STATUS SCU_ECAT0CON_PORT0_LINKB
+#elif GET_GPIO(ECAT_P0_LINK_STATUS) == (GPIO_PORT9 | GPIO_PIN10)
+ #define P0_LINK_STATUS SCU_ECAT0CON_PORT0_LINKC
+#else
+ #error "EtherCAT : Unknown P0_LINK_STATUS configuration"
+#endif
+
+/* Port 0 TX CLK */
+
+#if GET_GPIO(ECAT_P0_TX_CLK) == (GPIO_PORT1 | GPIO_PIN0)
+ #define P0_TX_CLK SCU_ECAT0CON_PORT0_TX_CLKA
+#elif GET_GPIO(ECAT_P0_TX_CLK) == (GPIO_PORT5 | GPIO_PIN5)
+ #define P0_TX_CLK SCU_ECAT0CON_PORT0_TX_CLKB
+#elif GET_GPIO(ECAT_P0_TX_CLK) == (GPIO_PORT9 | GPIO_PIN1)
+ #define P0_TX_CLK SCU_ECAT0CON_PORT0_TX_CLKC
+#else
+ #error "EtherCAT : Unknown P0_TX_CLK configuration"
+#endif
+
+#else /* not CONFIG_XMC4_ECAT_P0 */
+/* When port 0 is not available, the unused MII need to be tied
+ * to not connected pins.
+ */
+#define P0_RXD0 SCU_ECAT0CON_PORT0_RXD0D;
+#define P0_RXD1 SCU_ECAT0CON_PORT0_RXD1D;
+#define P0_RXD2 SCU_ECAT0CON_PORT0_RXD2D;
+#define P0_RXD3 SCU_ECAT0CON_PORT0_RXD3D;
+#define P0_RX_CLK SCU_ECAT0CON_PORT0_RX_CLKD;
+#define P0_RX_DV SCU_ECAT0CON_PORT0_RX_DVD;
+#define P0_RX_ERR SCU_ECAT0CON_PORT0_RX_ERRD;
+#define P0_LINK_STATUS SCU_ECAT0CON_PORT0_LINKB;
+#define P0_TX_CLK SCU_ECAT0CON_PORT0_TX_CLKD;
+#endif /* CONFIG_XMC4_ECAT_P0 */
+
+#if defined(CONFIG_XMC4_ECAT_P1)
+
+/* Port 1 RX D0 */
+
+#if GET_GPIO(ECAT_P1_RXD0) == (GPIO_PORT0 | GPIO_PIN11)
+ #define P1_RXD0 SCU_ECAT0CON_PORT1_RXD0A
+#elif GET_GPIO(ECAT_P1_RXD0) == (GPIO_PORT14 | GPIO_PIN7)
+ #define P1_RXD0 SCU_ECAT0CON_PORT1_RXD0B
+#elif GET_GPIO(ECAT_P1_RXD0) == (GPIO_PORT8 | GPIO_PIN4)
+ #define P1_RXD0 SCU_ECAT0CON_PORT1_RXD0C
+#else
+ #error "EtherCAT : Unknown P1_RXD0 configuration"
+#endif
+
+/* Port 1 RX D1 */
+
+#if GET_GPIO(ECAT_P1_RXD1) == (GPIO_PORT0 | GPIO_PIN6)
+ #define P1_RXD1 SCU_ECAT0CON_PORT1_RXD1A
+#elif GET_GPIO(ECAT_P1_RXD1) == (GPIO_PORT14 | GPIO_PIN12)
+ #define P1_RXD1 SCU_ECAT0CON_PORT1_RXD1B
+#elif GET_GPIO(ECAT_P1_RXD1) == (GPIO_PORT8 | GPIO_PIN5)
+ #define P1_RXD1 SCU_ECAT0CON_PORT1_RXD1C
+#else
+ #error "EtherCAT : Unknown P1_RXD1 configuration"
+#endif
+
+/* Port 1 RX D2 */
+
+#if GET_GPIO(ECAT_P1_RXD2) == (GPIO_PORT0 | GPIO_PIN5)
+ #define P1_RXD2 SCU_ECAT0CON_PORT1_RXD2A
+#elif GET_GPIO(ECAT_P1_RXD2) == (GPIO_PORT14 | GPIO_PIN13)
+ #define P1_RXD2 SCU_ECAT0CON_PORT1_RXD2B
+#elif GET_GPIO(ECAT_P1_RXD2) == (GPIO_PORT8 | GPIO_PIN6)
+ #define P1_RXD2 SCU_ECAT0CON_PORT1_RXD2C
+#else
+ #error "EtherCAT : Unknown P1_RXD2 configuration"
+#endif
+
+/* Port 1 RX D3 */
+
+#if GET_GPIO(ECAT_P1_RXD3) == (GPIO_PORT0 | GPIO_PIN4)
+ #define P1_RXD3 SCU_ECAT0CON_PORT1_RXD3A
+#elif GET_GPIO(ECAT_P1_RXD3) == (GPIO_PORT14 | GPIO_PIN14)
+ #define P1_RXD3 SCU_ECAT0CON_PORT1_RXD3B
+#elif GET_GPIO(ECAT_P1_RXD3) == (GPIO_PORT8 | GPIO_PIN7)
+ #define P1_RXD3 SCU_ECAT0CON_PORT1_RXD3C
+#else
+ #error "EtherCAT : Unknown P1_RXD3 configuration"
+#endif
+
+/* Port 1 RX CLK */
+
+#if GET_GPIO(ECAT_P1_RX_CLK) == (GPIO_PORT0 | GPIO_PIN1)
+ #define P1_RX_CLK SCU_ECAT0CON_PORT1_RX_CLKA
+#elif GET_GPIO(ECAT_P1_RX_CLK) == (GPIO_PORT14 | GPIO_PIN6)
+ #define P1_RX_CLK SCU_ECAT0CON_PORT1_RX_CLKB
+#elif GET_GPIO(ECAT_P1_RX_CLK) == (GPIO_PORT8 | GPIO_PIN10)
+ #define P1_RX_CLK SCU_ECAT0CON_PORT1_RX_CLKC
+#else
+ #error "EtherCAT : Unknown P1_RX_CLK configuration"
+#endif
+
+/* Port 1 RX DV */
+
+#if GET_GPIO(ECAT_P1_RX_DV) == (GPIO_PORT0 | GPIO_PIN9)
+ #define P1_RX_DV SCU_ECAT0CON_PORT1_RX_DVA
+#elif GET_GPIO(ECAT_P1_RX_DV) == (GPIO_PORT14 | GPIO_PIN15)
+ #define P1_RX_DV SCU_ECAT0CON_PORT1_RX_DVB
+#elif GET_GPIO(ECAT_P1_RX_DV) == (GPIO_PORT8 | GPIO_PIN11)
+ #define P1_RX_DV SCU_ECAT0CON_PORT1_RX_DVC
+#else
+ #error "EtherCAT : Unknown P1_RX_DV configuration"
+#endif
+
+/* Port 1 RX ERR */
+
+#if GET_GPIO(ECAT_P1_RX_ERR) == (GPIO_PORT3 | GPIO_PIN5)
+ #define P1_RX_ERR SCU_ECAT0CON_PORT1_RX_ERRA
+#elif GET_GPIO(ECAT_P1_RX_ERR) == (GPIO_PORT15 | GPIO_PIN2)
+ #define P1_RX_ERR SCU_ECAT0CON_PORT1_RX_ERRB
+#elif GET_GPIO(ECAT_P1_RX_ERR) == (GPIO_PORT8 | GPIO_PIN9)
+ #define P1_RX_ERR SCU_ECAT0CON_PORT1_RX_ERRC
+#else
+ #error "EtherCAT : Unknown P1_RX_ERR configuration"
+#endif
+
+/* Port 1 LINK */
+
+#if GET_GPIO(ECAT_P1_LINK_STATUS) == (GPIO_PORT3 | GPIO_PIN4)
+ #define P1_LINK_STATUS SCU_ECAT0CON_PORT1_LINKA
+#elif GET_GPIO(ECAT_P1_LINK_STATUS) == (GPIO_PORT15 | GPIO_PIN3)
+ #define P1_LINK_STATUS SCU_ECAT0CON_PORT1_LINKB
+#elif GET_GPIO(ECAT_P1_LINK_STATUS) == (GPIO_PORT9 | GPIO_PIN11)
+ #define P1_LINK_STATUS SCU_ECAT0CON_PORT1_LINKC
+#else
+ #error "EtherCAT : Unknown P1_LINK_STATUS configuration"
+#endif
+
+/* Port 1 TX CLK */
+
+#if GET_GPIO(ECAT_P1_TX_CLK) == (GPIO_PORT0 | GPIO_PIN10)
+ #define P1_TX_CLK SCU_ECAT0CON_PORT1_TX_CLKA
+#elif GET_GPIO(ECAT_P1_TX_CLK) == (GPIO_PORT5 | GPIO_PIN9)
+ #define P1_TX_CLK SCU_ECAT0CON_PORT1_TX_CLKB
+#elif GET_GPIO(ECAT_P1_TX_CLK) == (GPIO_PORT9 | GPIO_PIN0)
+ #define P1_TX_CLK SCU_ECAT0CON_PORT1_TX_CLKC
+#else
+ #error "EtherCAT : Unknown P1_TX_CLK configuration"
+#endif
+
+#else /* not CONFIG_XMC4_ECAT_P1 */
+/* When port 1 is not available, the unused MII need to be tied
+ * to not connected pins.
+ */
+#define P1_RXD0 SCU_ECAT0CON_PORT1_RXD0D;
+#define P1_RXD1 SCU_ECAT0CON_PORT1_RXD1D;
+#define P1_RXD2 SCU_ECAT0CON_PORT1_RXD2D;
+#define P1_RXD3 SCU_ECAT0CON_PORT1_RXD3D;
+#define P1_RX_CLK SCU_ECAT0CON_PORT1_RX_CLKD;
+#define P1_RX_DV SCU_ECAT0CON_PORT1_RX_DVD;
+#define P1_RX_ERR SCU_ECAT0CON_PORT1_RX_ERRD;
+#define P1_LINK_STATUS SCU_ECAT0CON_PORT1_LINKB;
+#define P1_TX_CLK SCU_ECAT0CON_PORT1_TX_CLKD;
+#endif /* CONFIG_XMC4_ECAT_P1 */
+
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -93,10 +361,16 @@ void xmc4_ecat_initialize()
xmc4_gpio_config(ECAT_MCLK);
xmc4_gpio_config(ECAT_PHY_RESET);
- /* configure PLL */
+ /* Configure clocks */
+
+#ifndef BOARD_ENABLE_USBPLL
+# error "EtherCAT need USBPLL clock enabled !"
+#endif
- #define SCU_ECATCLKCR_PLL ((0 << 16) | (1 << 0))
- putreg32(SCU_ECATCLKCR_PLL, XMC4_SCU_ECATCLKCR);
+ uint32_t ecatclkcr = 0;
+ ecatclkcr |= SCU_ECATCLKCR_ECATSEL_FPLLUSB;
+ ecatclkcr |= (BOARD_ECAT_DIV << SCU_ECATCLKCR_ECADIV_SHIFT);
+ putreg32(ecatclkcr, XMC4_SCU_ECATCLKCR);
/* ECAT reset */
@@ -129,581 +403,37 @@ void xmc4_ecat_initialize_port_control()
{
/* common */
- uint32_t mdio_conf = 0;
- switch (ECAT_MDO & (GPIO_PORT_MASK | GPIO_PIN_MASK))
- {
- case GPIO_PORT0 | GPIO_PIN12:
- {
- mdio_conf = SCU_ECAT0CON_MDIOA;
- break;
- }
-
- case GPIO_PORT4 | GPIO_PIN2:
- {
- mdio_conf = SCU_ECAT0CON_MDIOB;
- break;
- }
-
- case GPIO_PORT9 | GPIO_PIN7:
- {
- mdio_conf = SCU_ECAT0CON_MDIOC;
- break;
- }
-
- default:
- {
- nerr("Unknown mdio config \n");
- }
- }
-
- uint32_t ecat0_con_conf = 0;
- ecat0_con_conf |= SCU_ECAT0CON_PHY_OFFSET;
- ecat0_con_conf |= SCU_ECAT0CON_ECATRSTEN;
- ecat0_con_conf |= mdio_conf;
+ uint32_t ecat0_con_conf = 0; /* Default value to
0x0000 0000 but described here for reference */
+ ecat0_con_conf |= 0 << SCU_ECAT0CON_ECATRSTEN_SHIFT; /* Reset request by
master disabled */
+ ecat0_con_conf |= 0 << SCU_ECAT0CON_PHY_OFFSET_SHIFT; /* Offset of the PHY
address offset (port 0) */
+ ecat0_con_conf |= MDIO; /* MDIO input select */
+ putreg32(ecat0_con_conf, XMC4_SCU_ECAT0CON);
/* port0 */
- uint32_t port0_rxd0_conf = 0;
- switch (ECAT_P0_RXD0 & (GPIO_PORT_MASK | GPIO_PIN_MASK))
- {
- case GPIO_PORT1 | GPIO_PIN4:
- {
- port0_rxd0_conf = SCU_ECAT0CON_PORT0_RXD0A;
- break;
- }
-
- case GPIO_PORT5 | GPIO_PIN0:
- {
- port0_rxd0_conf = SCU_ECAT0CON_PORT0_RXD0B;
- break;
- }
-
- case GPIO_PORT7 | GPIO_PIN4:
- {
- port0_rxd0_conf = SCU_ECAT0CON_PORT0_RXD0C;
- break;
- }
-
- default:
- {
- nerr("Unknown port0_rxd0 config \n");
- }
- }
-
- uint32_t port0_rxd1_conf = 0;
- switch (ECAT_P0_RXD1 & (GPIO_PORT_MASK | GPIO_PIN_MASK))
- {
- case GPIO_PORT1 | GPIO_PIN5:
- {
- port0_rxd1_conf = SCU_ECAT0CON_PORT0_RXD1A;
- break;
- }
-
- case GPIO_PORT5 | GPIO_PIN1:
- {
- port0_rxd1_conf = SCU_ECAT0CON_PORT0_RXD1B;
- break;
- }
-
- case GPIO_PORT7 | GPIO_PIN5:
- {
- port0_rxd1_conf = SCU_ECAT0CON_PORT0_RXD1C;
- break;
- }
-
- default:
- {
- nerr("Unknown port0_rxd1 config \n");
- }
- }
-
- uint32_t port0_rxd2_conf = 0;
- switch (ECAT_P0_RXD2 & (GPIO_PORT_MASK | GPIO_PIN_MASK))
- {
- case GPIO_PORT1 | GPIO_PIN10:
- {
- port0_rxd2_conf = SCU_ECAT0CON_PORT0_RXD2A;
- break;
- }
-
- case GPIO_PORT5 | GPIO_PIN2:
- {
- port0_rxd2_conf = SCU_ECAT0CON_PORT0_RXD2B;
- break;
- }
-
- case GPIO_PORT7 | GPIO_PIN6:
- {
- port0_rxd2_conf = SCU_ECAT0CON_PORT0_RXD2C;
- break;
- }
-
- default:
- {
- nerr("Unknown port0_rxd2 config \n");
- }
- }
-
- uint32_t port0_rxd3_conf = 0;
- switch (ECAT_P0_RXD3 & (GPIO_PORT_MASK | GPIO_PIN_MASK))
- {
- case GPIO_PORT1 | GPIO_PIN11:
- {
- port0_rxd3_conf = SCU_ECAT0CON_PORT0_RXD3A;
- break;
- }
-
- case GPIO_PORT5 | GPIO_PIN7:
- {
- port0_rxd3_conf = SCU_ECAT0CON_PORT0_RXD3B;
- break;
- }
-
- case GPIO_PORT7 | GPIO_PIN7:
- {
- port0_rxd3_conf = SCU_ECAT0CON_PORT0_RXD3C;
- break;
- }
-
- default:
- {
- nerr("Unknown port0_rxd2 config \n");
- }
- }
-
- uint32_t port0_rx_clk_conf = 0;
- switch (ECAT_P0_RX_CLK & (GPIO_PORT_MASK | GPIO_PIN_MASK))
- {
- case GPIO_PORT1 | GPIO_PIN1:
- {
- port0_rx_clk_conf = SCU_ECAT0CON_PORT0_RX_CLKA;
- break;
- }
-
- case GPIO_PORT5 | GPIO_PIN4:
- {
- port0_rx_clk_conf = SCU_ECAT0CON_PORT0_RX_CLKB;
- break;
- }
-
- case GPIO_PORT7 | GPIO_PIN10:
- {
- port0_rx_clk_conf = SCU_ECAT0CON_PORT0_RX_CLKC;
- break;
- }
-
- default:
- {
- nerr("Unknown port0_rx_clk config \n");
- }
- }
-
- uint32_t port0_rx_dv_conf = 0;
- switch (ECAT_P0_RX_DV & (GPIO_PORT_MASK | GPIO_PIN_MASK))
- {
- case GPIO_PORT1 | GPIO_PIN9:
- {
- port0_rx_dv_conf = SCU_ECAT0CON_PORT0_RX_DVA;
- break;
- }
-
- case GPIO_PORT5 | GPIO_PIN6:
- {
- port0_rx_dv_conf = SCU_ECAT0CON_PORT0_RX_DVB;
- break;
- }
-
- case GPIO_PORT7 | GPIO_PIN11:
- {
- port0_rx_dv_conf = SCU_ECAT0CON_PORT0_RX_DVC;
- break;
- }
-
- default:
- {
- nerr("Unknown port0_rx_dv config \n");
- }
- }
-
- uint32_t port0_rx_err_conf = 0;
- switch (ECAT_P0_RX_ERR & (GPIO_PORT_MASK | GPIO_PIN_MASK))
- {
- case GPIO_PORT4 | GPIO_PIN0:
- {
- port0_rx_err_conf = SCU_ECAT0CON_PORT0_RX_ERRA;
- break;
- }
-
- case GPIO_PORT2 | GPIO_PIN6:
- {
- port0_rx_err_conf = SCU_ECAT0CON_PORT0_RX_ERRB;
- break;
- }
-
- case GPIO_PORT7 | GPIO_PIN9:
- {
- port0_rx_err_conf = SCU_ECAT0CON_PORT0_RX_ERRC;
- break;
- }
-
- default:
- {
- nerr("Unknown port0_rx_err config \n");
- }
- }
-
- uint32_t port0_link_conf = 0;
- switch (ECAT_P0_LINK_STATUS & (GPIO_PORT_MASK | GPIO_PIN_MASK))
- {
- case GPIO_PORT4 | GPIO_PIN1:
- {
- port0_link_conf = SCU_ECAT0CON_PORT0_LINKA;
- break;
- }
-
- case GPIO_PORT1 | GPIO_PIN15:
- {
- port0_link_conf = SCU_ECAT0CON_PORT0_LINKB;
- break;
- }
-
- case GPIO_PORT9 | GPIO_PIN10:
- {
- port0_link_conf = SCU_ECAT0CON_PORT0_LINKC;
- break;
- }
-
- default:
- {
- nerr("Unknown port0_link config \n");
- }
- }
-
- uint32_t port0_tx_clk_conf = 0;
- switch (ECAT_P0_TX_CLK & (GPIO_PORT_MASK | GPIO_PIN_MASK))
- {
- case GPIO_PORT1 | GPIO_PIN0:
- {
- port0_tx_clk_conf = SCU_ECAT0CON_PORT0_TX_CLKA;
- break;
- }
-
- case GPIO_PORT5 | GPIO_PIN5:
- {
- port0_tx_clk_conf = SCU_ECAT0CON_PORT0_TX_CLKB;
- break;
- }
-
- case GPIO_PORT9 | GPIO_PIN1:
- {
- port0_tx_clk_conf = SCU_ECAT0CON_PORT0_TX_CLKC;
- break;
- }
-
- default:
- {
- nerr("Unknown port0_tx_clk config \n");
- }
- }
-
uint32_t ecat0_port0_conf = 0;
-#ifndef CONFIG_XMC4_ECAT_P0
- /* When port 0 is not available, the unused MII need to be tied
- * to not connected pins.
- */
-
- port0_rxd0_conf = SCU_ECAT0CON_PORT0_RXD0D;
- port0_rxd1_conf = SCU_ECAT0CON_PORT0_RXD1D;
- port0_rxd2_conf = SCU_ECAT0CON_PORT0_RXD2D;
- port0_rxd3_conf = SCU_ECAT0CON_PORT0_RXD3D;
- port0_rx_clk_conf = SCU_ECAT0CON_PORT0_RX_CLKD;
- port0_rx_dv_conf = SCU_ECAT0CON_PORT0_RX_DVD;
- port0_rx_err_conf = SCU_ECAT0CON_PORT0_RX_ERRD;
- port0_link_conf = SCU_ECAT0CON_PORT0_LINKB;
- port0_tx_clk_conf = SCU_ECAT0CON_PORT0_TX_CLKD;
-#endif
- ecat0_port0_conf |= port0_rxd0_conf;
- ecat0_port0_conf |= port0_rxd1_conf;
- ecat0_port0_conf |= port0_rxd2_conf;
- ecat0_port0_conf |= port0_rxd3_conf;
- ecat0_port0_conf |= port0_rx_clk_conf;
- ecat0_port0_conf |= port0_rx_dv_conf;
- ecat0_port0_conf |= port0_rx_err_conf;
- ecat0_port0_conf |= port0_link_conf;
- ecat0_port0_conf |= port0_tx_clk_conf;
-
+ ecat0_port0_conf |= P0_RXD0;
+ ecat0_port0_conf |= P0_RXD1;
+ ecat0_port0_conf |= P0_RXD2;
+ ecat0_port0_conf |= P0_RXD3;
+ ecat0_port0_conf |= P0_RX_CLK;
+ ecat0_port0_conf |= P0_RX_DV;
+ ecat0_port0_conf |= P0_RX_ERR;
+ ecat0_port0_conf |= P0_LINK_STATUS;
+ ecat0_port0_conf |= P0_TX_CLK;
putreg32(ecat0_port0_conf, XMC4_SCU_ECAT0CONP0);
/* port 1 */
- uint32_t port1_rxd0_conf = 0;
- switch (ECAT_P1_RXD0 & (GPIO_PORT_MASK | GPIO_PIN_MASK))
- {
- case GPIO_PORT0 | GPIO_PIN11:
- {
- port1_rxd0_conf = SCU_ECAT0CON_PORT1_RXD0A;
- break;
- }
-
- case GPIO_PORT14 | GPIO_PIN7:
- {
- port1_rxd0_conf = SCU_ECAT0CON_PORT1_RXD0B;
- break;
- }
-
- case GPIO_PORT8 | GPIO_PIN4:
- {
- port1_rxd0_conf = SCU_ECAT0CON_PORT1_RXD0C;
- break;
- }
-
- default:
- {
- nerr("Unknown port1_rxd0 config \n");
- }
- }
-
- uint32_t port1_rxd1_conf = 0;
- switch (ECAT_P1_RXD1 & (GPIO_PORT_MASK | GPIO_PIN_MASK))
- {
- case GPIO_PORT0 | GPIO_PIN6:
- {
- port1_rxd1_conf = SCU_ECAT0CON_PORT1_RXD1A;
- break;
- }
-
- case GPIO_PORT14 | GPIO_PIN12:
- {
- port1_rxd1_conf = SCU_ECAT0CON_PORT1_RXD1B;
- break;
- }
-
- case GPIO_PORT8 | GPIO_PIN5:
- {
- port1_rxd1_conf = SCU_ECAT0CON_PORT1_RXD1C;
- break;
- }
-
- default:
- {
- nerr("Unknown port1_rxd1 config \n");
- }
- }
-
- uint32_t port1_rxd2_conf = 0;
- switch (ECAT_P1_RXD2 & (GPIO_PORT_MASK | GPIO_PIN_MASK))
- {
- case GPIO_PORT0 | GPIO_PIN5:
- {
- port1_rxd2_conf = SCU_ECAT0CON_PORT1_RXD2A;
- break;
- }
-
- case GPIO_PORT14 | GPIO_PIN13:
- {
- port1_rxd2_conf = SCU_ECAT0CON_PORT1_RXD2B;
- break;
- }
-
- case GPIO_PORT8 | GPIO_PIN6:
- {
- port1_rxd2_conf = SCU_ECAT0CON_PORT1_RXD2C;
- break;
- }
-
- default:
- {
- nerr("Unknown port1_rxd2 config \n");
- }
- }
-
- uint32_t port1_rxd3_conf = 0;
- switch (ECAT_P1_RXD3 & (GPIO_PORT_MASK | GPIO_PIN_MASK))
- {
- case GPIO_PORT0 | GPIO_PIN4:
- {
- port1_rxd3_conf = SCU_ECAT0CON_PORT1_RXD3A;
- break;
- }
-
- case GPIO_PORT14 | GPIO_PIN14:
- {
- port1_rxd3_conf = SCU_ECAT0CON_PORT1_RXD3B;
- break;
- }
-
- case GPIO_PORT8 | GPIO_PIN7:
- {
- port1_rxd3_conf = SCU_ECAT0CON_PORT1_RXD3C;
- break;
- }
-
- default:
- {
- nerr("Unknown port1_rxd3 config \n");
- }
- }
-
- uint32_t port1_rx_clk_conf = 0;
- switch (ECAT_P1_RX_CLK & (GPIO_PORT_MASK | GPIO_PIN_MASK))
- {
- case GPIO_PORT0 | GPIO_PIN1:
- {
- port1_rx_clk_conf = SCU_ECAT0CON_PORT1_RX_CLKA;
- break;
- }
-
- case GPIO_PORT14 | GPIO_PIN6:
- {
- port1_rx_clk_conf = SCU_ECAT0CON_PORT1_RX_CLKB;
- break;
- }
-
- case GPIO_PORT8 | GPIO_PIN10:
- {
- port1_rx_clk_conf = SCU_ECAT0CON_PORT1_RX_CLKC;
- break;
- }
-
- default:
- {
- nerr("Unknown port1_rx_clk config \n");
- }
- }
-
- uint32_t port1_rx_dv_conf = 0;
- switch (ECAT_P1_RX_DV & (GPIO_PORT_MASK | GPIO_PIN_MASK))
- {
- case GPIO_PORT0 | GPIO_PIN9:
- {
- port1_rx_dv_conf = SCU_ECAT0CON_PORT1_RX_DVA;
- break;
- }
-
- case GPIO_PORT14 | GPIO_PIN15:
- {
- port1_rx_dv_conf = SCU_ECAT0CON_PORT1_RX_DVB;
- break;
- }
-
- case GPIO_PORT8 | GPIO_PIN11:
- {
- port1_rx_dv_conf = SCU_ECAT0CON_PORT1_RX_DVC;
- break;
- }
-
- default:
- {
- nerr("Unknown port1_rx_dv config \n");
- }
- }
-
- uint32_t port1_link_conf = 0;
- switch (ECAT_P1_LINK_STATUS & (GPIO_PORT_MASK | GPIO_PIN_MASK))
- {
- case GPIO_PORT3 | GPIO_PIN4:
- {
- port1_link_conf = SCU_ECAT0CON_PORT1_LINKA;
- break;
- }
-
- case GPIO_PORT15 | GPIO_PIN3:
- {
- port1_link_conf = SCU_ECAT0CON_PORT1_LINKB;
- break;
- }
-
- case GPIO_PORT9 | GPIO_PIN11:
- {
- port1_link_conf = SCU_ECAT0CON_PORT1_LINKC;
- break;
- }
-
- default:
- {
- nerr("Unknown port1_link config \n");
- }
- }
-
- uint32_t port1_tx_clk_conf = 0;
- switch (ECAT_P1_TX_CLK & (GPIO_PORT_MASK | GPIO_PIN_MASK))
- {
- case GPIO_PORT0 | GPIO_PIN10:
- {
- port1_tx_clk_conf = SCU_ECAT0CON_PORT1_TX_CLKA;
- break;
- }
-
- case GPIO_PORT5 | GPIO_PIN9:
- {
- port1_tx_clk_conf = SCU_ECAT0CON_PORT1_TX_CLKB;
- break;
- }
-
- case GPIO_PORT9 | GPIO_PIN0:
- {
- port1_tx_clk_conf = SCU_ECAT0CON_PORT1_TX_CLKC;
- break;
- }
-
- default:
- {
- nerr("Unknown port1_tx_clk config \n");
- }
- }
-
- uint32_t port1_rx_err_conf = 0;
- switch (ECAT_P1_RX_ERR & (GPIO_PORT_MASK | GPIO_PIN_MASK))
- {
- case GPIO_PORT3 | GPIO_PIN5:
- {
- port1_rx_err_conf = SCU_ECAT0CON_PORT1_RX_ERRA;
- break;
- }
-
- case GPIO_PORT15 | GPIO_PIN2:
- {
- port1_rx_err_conf = SCU_ECAT0CON_PORT1_RX_ERRB;
- break;
- }
-
- case GPIO_PORT8 | GPIO_PIN9:
- {
- port1_rx_err_conf = SCU_ECAT0CON_PORT1_RX_ERRC;
- break;
- }
-
- default:
- {
- nerr("Unknown port1_rx_err config \n");
- }
- }
-
uint32_t ecat0_port1_conf = 0;
-#ifndef CONFIG_XMC4_ECAT_P1
- /* When port 1 is not available, the unused MII need to be tied
- * to not connected pins.
- */
-
- port1_rxd0_conf = SCU_ECAT0CON_PORT1_RXD0D;
- port1_rxd1_conf = SCU_ECAT0CON_PORT1_RXD1D;
- port1_rxd2_conf = SCU_ECAT0CON_PORT1_RXD2D;
- port1_rxd3_conf = SCU_ECAT0CON_PORT1_RXD3D;
- port1_rx_clk_conf = SCU_ECAT0CON_PORT1_RX_CLKD;
- port1_rx_dv_conf = SCU_ECAT0CON_PORT1_RX_DVD;
- port1_rx_err_conf = SCU_ECAT0CON_PORT1_RX_ERRD;
- port1_link_conf = SCU_ECAT0CON_PORT1_LINKB;
- port1_tx_clk_conf = SCU_ECAT0CON_PORT1_TX_CLKD;
-#endif
- ecat0_port1_conf |= port1_rxd0_conf;
- ecat0_port1_conf |= port1_rxd1_conf;
- ecat0_port1_conf |= port1_rxd2_conf;
- ecat0_port1_conf |= port1_rxd3_conf;
- ecat0_port1_conf |= port1_rx_clk_conf;
- ecat0_port1_conf |= port1_rx_dv_conf;
- ecat0_port1_conf |= port1_rx_err_conf;
- ecat0_port1_conf |= port1_link_conf;
- ecat0_port1_conf |= port1_tx_clk_conf;
-
+ ecat0_port1_conf |= P1_RXD0;
+ ecat0_port1_conf |= P1_RXD1;
+ ecat0_port1_conf |= P1_RXD2;
+ ecat0_port1_conf |= P1_RXD3;
+ ecat0_port1_conf |= P1_RX_CLK;
+ ecat0_port1_conf |= P1_RX_DV;
+ ecat0_port1_conf |= P1_RX_ERR;
+ ecat0_port1_conf |= P1_LINK_STATUS;
+ ecat0_port1_conf |= P1_TX_CLK;
putreg32(ecat0_port1_conf, XMC4_SCU_ECAT0CONP1);
}
diff --git a/arch/arm/src/xmc4/xmc4_gpio.h b/arch/arm/src/xmc4/xmc4_gpio.h
index 5360950d730..a8d120da669 100644
--- a/arch/arm/src/xmc4/xmc4_gpio.h
+++ b/arch/arm/src/xmc4/xmc4_gpio.h
@@ -125,7 +125,7 @@
* .... .... ..CC ..... .... .... .... ....
*/
-#define GPIO_PINCTRL_SHIFT (20) /* Bits 20-21: Pad driver
strength */
+#define GPIO_PINCTRL_SHIFT (20) /* Bits 20-21: Pin Control */
#define GPIO_PINCTRL_MASK (3 <<
GPIO_PINCTRL_SHIFT)
/* See chip/xmc4_ports.h for the PDR definitions */
diff --git a/boards/arm/xmc4/xmc4500-relax/include/board.h
b/boards/arm/xmc4/xmc4500-relax/include/board.h
index 924ba96b7b1..ba356ef9f89 100644
--- a/boards/arm/xmc4/xmc4500-relax/include/board.h
+++ b/boards/arm/xmc4/xmc4500-relax/include/board.h
@@ -101,13 +101,13 @@
/* 120 MHz
*
- * fVCO = 12MHz * 40 / 2 = 480MHz
- * fPLL = 480MHz / 2 = 240MHz
- * fSYS = fPLL / 2 = 120MHz
- * fCCU = fSYS / 2 = 60MHz
- * fCPU = fSYS / 1 = 120MHz
- * fPB = fCPU / 2 = 60MHz
- * fETH = fSYS / 2 = 60MHz
+ * fVCO = 12MHz * 40 / 1 = 480MHz
+ * fPLL = 480MHz / 4 = 120MHz
+ * fSYS = fPLL / 1 = 120MHz
+ * fCCU = fSYS / 2 = 60MHz
+ * fCPU = fSYS / 1 = 120MHz
+ * fPERIPH = fCPU / 2 = 60MHz
+ * fETH = fSYS / 2 = 60MHz
*/
# define BOARD_PLL_NDIV 40
@@ -160,9 +160,6 @@
# define BOARD_WDTDIV 1
# define BOARD_WDT_FREQUENCY 24000000
-# define BOARD_EXT_SOURCE EXT_CLKSRC_FPLL
-# define BOARD_PLL_ECKDIV 480 /* [1,512] */
-
# define kHz_1 1000
# define MHz_1 (kHz_1 * kHz_1)
# define MHz_50 ( 50 * MHz_1)
@@ -206,12 +203,10 @@
# define EXTCLK_PIN_P1_15 15
# define BOARD_EXTCLK_PIN EXTCLK_PIN_P0_8
# define BOARD_EXT_SOURCE EXT_CLKSRC_FPLL
-# define BOARD_EXT_FREQUENCY (250 * kHz_1) /* Desired output freq */
-# define BOARD_EXTDIV (BOARD_PLL_FREQUENCY / BOARD_EXT_FREQUENCY)
+# define BOARD_PLL_ECKDIV 480 /* [1,512] */
/* range check EXTDIV */
-
-# if BOARD_EXTDIV > 512
+# if BOARD_PLL_ECKDIV > 512
# error "EXTCLK Divisor out of range!"
# endif
#endif
@@ -235,8 +230,8 @@
*/
#undef BOARD_ENABLE_USBPLL
-#define BOARD_USB_PDIV 2
-#define BOARD_USB_NDIV 64
+#define BOARD_USBPLL_PDIV 2
+#define BOARD_USBPLL_NDIV 64
/* FLASH wait states */
diff --git a/boards/arm/xmc4/xmc4700-relax/include/board.h
b/boards/arm/xmc4/xmc4700-relax/include/board.h
index 81fd2a05838..ab708ba5f9b 100644
--- a/boards/arm/xmc4/xmc4700-relax/include/board.h
+++ b/boards/arm/xmc4/xmc4700-relax/include/board.h
@@ -97,13 +97,13 @@
/* 120 MHz
*
- * fVCO = 12MHz * 40 / 2 = 480MHz
- * fPLL = 480MHz / 2 = 240MHz
- * fSYS = fPLL / 2 = 120MHz
- * fCCU = fSYS / 2 = 60MHz
- * fCPU = fSYS / 1 = 120MHz
- * fPB = fCPU / 2 = 60MHz
- * fETH = fSYS / 2 = 60MHz
+ * fVCO = 12MHz * 40 / 1 = 480MHz
+ * fPLL = 480MHz / 4 = 120MHz
+ * fSYS = fPLL / 1 = 120MHz
+ * fCCU = fSYS / 2 = 60MHz
+ * fCPU = fSYS / 1 = 120MHz
+ * fPERIPH = fCPU / 2 = 60MHz
+ * fETH = fSYS / 2 = 60MHz
*/
# define BOARD_PLL_NDIV 40
@@ -156,9 +156,6 @@
# define BOARD_WDTDIV 1
# define BOARD_WDT_FREQUENCY 24000000
-# define BOARD_EXT_SOURCE EXT_CLKSRC_FPLL
-# define BOARD_PLL_ECKDIV 480 /* [1,512] */
-
# define kHz_1 1000
# define MHz_1 (kHz_1 * kHz_1)
# define MHz_50 ( 50 * MHz_1)
@@ -202,12 +199,10 @@
# define EXTCLK_PIN_P1_15 15
# define BOARD_EXTCLK_PIN EXTCLK_PIN_P0_8
# define BOARD_EXT_SOURCE EXT_CLKSRC_FPLL
-# define BOARD_EXT_FREQUENCY (250 * kHz_1) /* Desired output freq */
-# define BOARD_EXTDIV (BOARD_PLL_FREQUENCY / BOARD_EXT_FREQUENCY)
+# define BOARD_PLL_ECKDIV 480 /* [1,512] */
/* range check EXTDIV */
-
-# if BOARD_EXTDIV > 512
+# if BOARD_PLL_ECKDIV > 512
# error "EXTCLK Divisor out of range!"
# endif
#endif
@@ -224,15 +219,16 @@
/* USB PLL settings.
*
- * fUSBPLL = 48MHz and fUSBPLLVCO = 384 MHz
+ * fUSBPLL = fXTAL * N / 2P = 192MHz
+ * fUSB = fUSBPLL / USBDIV = 192MHz / 4 = 48 MHz
*
* Note: Implicit divider of 2 and fUSBPLLVCO >= 260 MHz and
* fUSBPLLVCO <= 520 MHz
*/
#undef BOARD_ENABLE_USBPLL
-#define BOARD_USB_PDIV 2
-#define BOARD_USB_NDIV 64
+#define BOARD_USBPLL_PDIV 2
+#define BOARD_USBPLL_NDIV 64
/* FLASH wait states */
@@ -301,7 +297,7 @@
#define BUTTON_0_BIT (1 << BUTTON_0)
#define BUTTON_1_BIT (1 << BUTTON_1)
-/* USIC0 ********************************************************************/
+/* USIC *********************************************************************/
/* USIC0 CH0 is used as UART0
*
diff --git a/boards/arm/xmc4/xmc4800-relax/include/board.h
b/boards/arm/xmc4/xmc4800-relax/include/board.h
index 8eb6e5742f7..57fdfa03c4a 100644
--- a/boards/arm/xmc4/xmc4800-relax/include/board.h
+++ b/boards/arm/xmc4/xmc4800-relax/include/board.h
@@ -91,19 +91,17 @@
#define BOARD_ENABLE_PLL 1 /* enable the PLL */
#define CPU_FREQ 120 /* MHz */
-/* TODO: Automate PLL calculations */
-
#if CPU_FREQ == 120
/* 120 MHz
*
- * fVCO = 12MHz * 40 / 2 = 480MHz
- * fPLL = 480MHz / 2 = 240MHz
- * fSYS = fPLL / 2 = 120MHz
- * fCCU = fSYS / 2 = 60MHz
- * fCPU = fSYS / 1 = 120MHz
- * fPB = fCPU / 2 = 60MHz
- * fETH = fSYS / 2 = 60MHz
+ * fVCO = 12MHz * 40 / 1 = 480MHz
+ * fPLL = 480MHz / 4 = 120MHz
+ * fSYS = fPLL / 1 = 120MHz
+ * fCCU = fSYS / 2 = 60MHz
+ * fCPU = fSYS / 1 = 120MHz
+ * fPERIPH = fCPU / 2 = 60MHz
+ * fETH = fSYS / 2 = 60MHz
*/
# define BOARD_PLL_NDIV 40
@@ -156,9 +154,6 @@
# define BOARD_WDTDIV 1
# define BOARD_WDT_FREQUENCY 24000000
-# define BOARD_EXT_SOURCE EXT_CLKSRC_FPLL
-# define BOARD_PLL_ECKDIV 480 /* [1,512] */
-
# define kHz_1 1000
# define MHz_1 (kHz_1 * kHz_1)
# define MHz_50 ( 50 * MHz_1)
@@ -195,19 +190,17 @@
/* EXT clock settings */
-#define BOARD_EXTCKL_ENABLE 1 /* 0 disables output */
+#define BOARD_EXTCKL_ENABLE 0 /* 0 disables output, P0.12 taken by
ECAT */
#if BOARD_EXTCKL_ENABLE
# define EXTCLK_PIN_P0_8 8
# define EXTCLK_PIN_P1_15 15
# define BOARD_EXTCLK_PIN EXTCLK_PIN_P0_8
# define BOARD_EXT_SOURCE EXT_CLKSRC_FPLL
-# define BOARD_EXT_FREQUENCY (250 * kHz_1) /* Desired output freq */
-# define BOARD_EXTDIV (BOARD_PLL_FREQUENCY / BOARD_EXT_FREQUENCY)
+# define BOARD_PLL_ECKDIV 480 /* [1,512] */
/* range check EXTDIV */
-
-# if BOARD_EXTDIV > 512
+# if BOARD_PLL_ECKDIV > 512
# error "EXTCLK Divisor out of range!"
# endif
#endif
@@ -224,15 +217,27 @@
/* USB PLL settings.
*
- * fUSBPLL = 48MHz and fUSBPLLVCO = 384 MHz
+ * fUSBPLLVCO = fXTAL * N / P = 12M * 100 / 3 = 400MHz
+ * fUSBPLL = fUSBPLLVCO / 2 = 200MHz
*
* Note: Implicit divider of 2 and fUSBPLLVCO >= 260 MHz and
* fUSBPLLVCO <= 520 MHz
*/
-#define BOARD_ENABLE_USBPLL
-#define BOARD_USB_PDIV 3
-#define BOARD_USB_NDIV 100
+#define BOARD_ENABLE_USBPLL
+#define BOARD_USBPLL_PDIV 3
+#define BOARD_USBPLL_NDIV 100
+
+/* ECAT clock
+ *
+ * fECAT = fUSBPLL / (ECATDIV + 1) = 200M / 2 = 100MHz
+ */
+
+#define BOARD_ECAT_DIV 1
+
+# if BOARD_ECAT_DIV > 3
+# error "ECADIV out of range! [0-3]"
+# endif
/* FLASH wait states */
@@ -301,7 +306,7 @@
#define BUTTON_0_BIT (1 << BUTTON_0)
#define BUTTON_1_BIT (1 << BUTTON_1)
-/* USIC0 ********************************************************************/
+/* Peripherals definitions **************************************************/
/* USIC0 CH0 is used as UART0
*
@@ -325,7 +330,9 @@
#define GPIO_SPI4_MISO (GPIO_U2C0_DX0C)
#define GPIO_SPI4_SCLK (GPIO_U2C0_SCLKOUT_1 | GPIO_PADA2_STRONGMEDIUM)
-/* ECAT0 configuration */
+/* ECAT0 configuration
+ * See XMC4800 Relax Board user manual for associated pinout.
+ */
#define ECAT_CLK_25 GPIO_ECAT_CLK_25_1
#define ECAT_LED_ERR GPIO_ECAT_LED_ERR
