This is an automated email from the ASF dual-hosted git repository.

xiaoxiang781216 pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git


The following commit(s) were added to refs/heads/master by this push:
     new 7f6a0a30dae boards/arm/stm32l4/b-l475e-iot01a: Add a QEMU nsh 
configuration.
7f6a0a30dae is described below

commit 7f6a0a30daeb724259b99b914f7e2fb075433889
Author: Marco Casaroli <[email protected]>
AuthorDate: Mon Aug 10 12:48:40 2026 +0200

    boards/arm/stm32l4/b-l475e-iot01a: Add a QEMU nsh configuration.
    
    QEMU's b-l475e-iot01a machine models the STM32L4x5 core peripherals, but
    not the QUADSPI controller or the on-board MX25R6435F flash.  The nsh
    configuration therefore panics during board bring-up, inside
    stm32_qspi_initialize() -> mx25rxx_initialize() -> qspi_command(), before
    the console has produced any output.
    
    Add a qemu configuration that is nsh without CONFIG_B_L475E_IOT01A_MTD_FLASH
    and the QSPI/MTD/SMARTFS chain that symbol selects.  It boots to an NSH
    prompt on USART1 under:
    
      qemu-system-arm -M b-l475e-iot01a -nographic -kernel nuttx
    
    Document the new configuration, including the fact that QEMU's STM32L4x5
    USART model never calls qemu_chr_fe_accept_input() after the guest reads
    RDR.  Console input consequently stalls after the first byte or two when a
    line is pasted or piped in, although typing at human speed works.
    
    Assisted-by: Claude Code:claude-opus-5
    Signed-off-by: Marco Casaroli <[email protected]>
---
 .../arm/stm32l4/boards/b-l475e-iot01a/index.rst    | 32 +++++++++++++++++
 .../stm32l4/b-l475e-iot01a/configs/qemu/defconfig  | 41 ++++++++++++++++++++++
 2 files changed, 73 insertions(+)

diff --git 
a/Documentation/platforms/arm/stm32l4/boards/b-l475e-iot01a/index.rst 
b/Documentation/platforms/arm/stm32l4/boards/b-l475e-iot01a/index.rst
index b21c1fa1a2c..e11ef4f6773 100644
--- a/Documentation/platforms/arm/stm32l4/boards/b-l475e-iot01a/index.rst
+++ b/Documentation/platforms/arm/stm32l4/boards/b-l475e-iot01a/index.rst
@@ -257,6 +257,38 @@ nsh:
 Configures the NuttShell (nsh) located at examples/nsh.  This
 configuration is focused on low level, command-line driver testing.
 
+qemu:
+-----
+
+The same NuttShell configuration as 'nsh', but targeted at the QEMU
+``b-l475e-iot01a`` machine instead of real hardware.  QEMU models the
+STM32L4x5 core peripherals (RCC, GPIO, EXTI, SYSCFG, USART) but does
+not model the QUADSPI controller or the on-board MX25R6435F flash, so
+this configuration drops the external flash stack that 'nsh' enables::
+
+    CONFIG_B_L475E_IOT01A_MTD_FLASH  (and the QSPI/MTD/SMARTFS chain it 
selects)
+
+Without that change the 'nsh' image panics during board bring-up, inside
+``stm32_qspi_initialize()`` -> ``mx25rxx_initialize()``, before the console
+ever produces output.
+
+Build and run it with::
+
+    tools/configure.sh b-l475e-iot01a:qemu
+    make
+    qemu-system-arm -M b-l475e-iot01a -nographic -kernel nuttx
+
+Console output appears on USART1, which the machine wires to the first
+serial port.  Exit QEMU with :kbd:`Ctrl-a x`.
+
+NOTE: QEMU's STM32L4x5 USART model never calls
+``qemu_chr_fe_accept_input()`` after the guest reads RDR.  Once a byte
+arrives while RXNE is still set, the chardev front end throttles and does
+not resume, so pasting or piping a line of input into the console stalls
+after the first character or two.  Typing at human speed works normally;
+scripted input needs a delay of a few hundred milliseconds between
+characters.
+
 spirit-6lowpan
 --------------
 
diff --git a/boards/arm/stm32l4/b-l475e-iot01a/configs/qemu/defconfig 
b/boards/arm/stm32l4/b-l475e-iot01a/configs/qemu/defconfig
new file mode 100644
index 00000000000..f3f74b72611
--- /dev/null
+++ b/boards/arm/stm32l4/b-l475e-iot01a/configs/qemu/defconfig
@@ -0,0 +1,41 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed 
.config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that 
includes your
+# modifications.
+#
+# CONFIG_NSH_ARGCAT is not set
+# CONFIG_NSH_CMDOPT_HEXDUMP is not set
+CONFIG_ARCH="arm"
+CONFIG_ARCH_BOARD="b-l475e-iot01a"
+CONFIG_ARCH_BOARD_B_L475E_IOT01A=y
+CONFIG_ARCH_CHIP="stm32l4"
+CONFIG_ARCH_CHIP_STM32=y
+CONFIG_ARCH_CHIP_STM32L475VG=y
+CONFIG_ARCH_CHIP_STM32L4=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_BOARD_LOOPSPERMSEC=8025
+CONFIG_BUILTIN=y
+CONFIG_FS_PROCFS=y
+CONFIG_HAVE_CXX=y
+CONFIG_HAVE_CXXINITIALIZE=y
+CONFIG_INIT_ENTRYPOINT="nsh_main"
+CONFIG_INTELHEX_BINARY=y
+CONFIG_LINE_MAX=64
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_READLINE=y
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_RAM_SIZE=114688
+CONFIG_RAM_START=0x20000000
+CONFIG_RAW_BINARY=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_WAITPID=y
+CONFIG_START_DAY=6
+CONFIG_START_MONTH=12
+CONFIG_START_YEAR=2011
+CONFIG_STM32_USART1=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_USART1_SERIAL_CONSOLE=y
+CONFIG_WATCHDOG=y

Reply via email to