ajlennon commented on PR #19858: URL: https://github.com/apache/nuttx/pull/19858#issuecomment-5307558815
## WIP verification update — SYS_PLL3 / ELE-TRDC ownership **Tip:** `d4ba1324ff6` (`arch/arm/imxrt: Initialize RT118x SYS_PLL3 clocks.`) ### What landed - ELE messaging over the secure MU (`0x57540000`) to transfer AON / MEGA / WAKEUP TRDC ownership to the Cortex-M33. - PLL LDO enable + fixed 480 MHz **SYS_PLL3** bring-up. - Roots after success: M33 = SYS_PLL3 / 2 (**240 MHz**); LPUART0102 = SYS_PLL3_DIV2 / 10 (**24 MHz** console retained). - Fail-closed: if ownership or PLL lock fails, startup stops rather than running the scheduler on RC24M with 240 MHz timing constants. - Status/error preserved in `g_imxrt118x_clock_status` / `g_imxrt118x_clock_error` outside the heap. ### Hardware smoke (FRDM-IMXRT1186, LinkServer RAM load, probe `WGUPS4RWFPGOT`) - NSH prompt reached; `uname -a` reports `frdm-imxrt1186`. - `g_imxrt118x_clock_status = 0x7f`, `g_imxrt118x_clock_error = 0`. - Live registers: `SYS_PLL3_CTRL=0x2020201b`, M33 root `0x00000201`, LPUART0102 root `0x00000209`. - `uptime` advances at ~1 s/tick with the 240 MHz SysTick constants. ### Honesty / still open - This is the maintainer “complete” bar for **autonomous SYS_PLL3 + ELE/TRDC ownership**, not a claim of full Zephyr-equivalent clock tree (SYS_PLL1/2, ARM PLL, full TRDC DAC/MRC/MBC policy, POR FlexSPI flash, or Ethernet/VPN). - ELE active-timer ping (24 h) is still application-side. - PR remains **[WIP]**. _Posted via Briar on behalf of Alex J Lennon._ -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
