jsanchez-2g opened a new pull request, #19978:
URL: https://github.com/apache/nuttx/pull/19978
Summary
The STM32H5 unique ID is stored in flash information memory, which cannot be
accessed while the instruction cache is enabled. Attempting to read it with
ICACHE enabled causes a bus fault.
Temporarily disable the instruction cache while reading the UID using 32-bit
accesses, then restore it only when it was originally enabled. This preserves
the caller's cache state and prevents the fault during UID access.
Impact
This change affects STM32H5 targets that enable CONFIG_STM32_ICACHE and call
stm32_get_uniqueid().
The existing cache state is preserved:
- If ICACHE is enabled, it is disabled for the UID read and then re-enabled.
- If ICACHE is already disabled, it remains disabled.
Other STM32 families and STM32H5 configurations without ICACHE are
unaffected. There are no configuration, API, documentation, or build-system
changes.
Testing
Host:
WSL2 Ubuntu 24.04
STM32 GNU Toolchain 13.2.1
Apache NuttX CI container
Clang 17.0.1
Target:
STM32H563ZI
ST-LINK/V2
STMicroelectronics OpenOCD
Static checks
The full commit-aware NuttX check passed:
$ ./tools/checkpatch.sh -c -u -m -g apache/master..HEAD
Used config files:
1: .codespellrc
✔️ All checks pass.
git diff --check also passed.
GNU build
Built nucleo-h563zi:nsh with CONFIG_STM32_ICACHE=y using the GNU EABI
toolchain:
CONFIG_ARM_TOOLCHAIN_GNU_EABI=y
CONFIG_ARCH_CHIP_STM32H5=y
CONFIG_STM32_ICACHE=y
Memory region Used Size Region Size %age Used
flash: 226256 B 2 MB 10.79%
sram: 9832 B 256 KB 3.75%
Clang build
Built nucleo-h563zi:nsh in the Apache NuttX CI container with Clang and
ICACHE enabled.
The board's GNU-specific software stack-check option was disabled and
LIBM_NONE selected for this cross-toolchain build:
CONFIG_ARM_TOOLCHAIN_CLANG=y
CONFIG_ARCH_TOOLCHAIN_CLANG=y
CONFIG_ARMV8M_STACKCHECK_NONE=y
CONFIG_LIBM_NONE=y
CONFIG_STM32_ICACHE=y
Memory region Used Size Region Size %age Used
flash: 187804 B 2 MB 8.96%
sram: 9800 B 256 KB 3.74%
The generated stm32_uid.o was inspected to confirm that it was compiled by
Clang 17.0.1.
Hardware validation
Before the change, calling stm32_get_uniqueid() with ICACHE enabled produced
a precise bus fault while accessing the UID address:
CFSR: 0x00008200
HFSR: 0x40000000
BFAR: 0x08fff800
After applying the change:
- The firmware reached its application entry point without a hard fault or
assertion.
- The UID was read successfully:
003A004D 31335107 36323839
- CFSR and HFSR remained clear.
- ICACHE_CR was 0x00000005 after the read, confirming that the previously
enabled instruction cache was restored.
Assisted-by: Codex:gpt-5
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