xiaoxiang781216 commented on code in PR #20125: URL: https://github.com/apache/nuttx/pull/20125#discussion_r3999193974
########## arch/risc-v/include/irq.h: ########## @@ -201,7 +201,26 @@ #define REG_INT_CTX_NDX 32 -#ifdef CONFIG_ARCH_RISCV_INTXCPT_EXTREGS +/* On a CLIC part, mcause carries mpp / mpie / mpil / interrupt -- state that + * mret consults -- so it must be saved and restored with the frame, not just + * read for dispatch. Uses the ARCH_RISCV_INTXCPT_EXTREGS extension slot, + * so REG_INT_CTX and everything below it keep their existing offsets. + */ + +#if defined(CONFIG_ARCH_CHIP_ESP32P4) && !defined(CONFIG_BUILD_FLAT) Review Comment: yes, please reference https://github.com/apache/nuttx/pull/20126. ########## arch/risc-v/src/common/riscv_swint.c: ########## @@ -137,6 +140,170 @@ uintptr_t dispatch_syscall(unsigned int nbr, uintptr_t parm1, } #endif +#ifdef CONFIG_RISCV_FRAME_TRACE Review Comment: yes, since it changes the common code and need more review. -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
