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commit e24158d38f7be36fa4026cb2c512396bbdc01461 Author: Jukka Laitinen <[email protected]> AuthorDate: Wed Sep 2 12:27:50 2026 +0300 arch/arm/imxrt: Initial support for OCOTP on imxrt1180 Support reading the OCOTP via the shadow register on imxrt chips with integrated ELE. On these chips, writing is done via ELE, this is not yet implemented. Signed-off-by: Jukka Laitinen <[email protected]> --- arch/arm/src/imxrt/hardware/imxrt_ocotp.h | 13 ++++++ .../src/imxrt/hardware/rt118x/imxrt118x_ocotp.h | 47 ++++++++++++++++++++++ arch/arm/src/imxrt/imxrt_ocotp.c | 47 +++++++++++++++++++++- 3 files changed, 106 insertions(+), 1 deletion(-) diff --git a/arch/arm/src/imxrt/hardware/imxrt_ocotp.h b/arch/arm/src/imxrt/hardware/imxrt_ocotp.h index 6a310a7b483..18dda8053ab 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_ocotp.h +++ b/arch/arm/src/imxrt/hardware/imxrt_ocotp.h @@ -36,6 +36,17 @@ #include <nuttx/config.h> #include "hardware/imxrt_memorymap.h" +#ifdef CONFIG_ARCH_FAMILY_IMXRT118x + +/* On chips fronted by the EdgeLock Enclave (e.g. RT1180) the OCOTP + * register layout differs and only a shadow-read window is exposed to + * the SoC; see hardware/rt118x/imxrt118x_ocotp.h for details. + */ + +# include "hardware/rt118x/imxrt118x_ocotp.h" + +#else + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -425,4 +436,6 @@ #define OCOTP_LOCK_FIELD_RETURN_MASK (15 << OCOTP_LOCK_FIELD_RETURN_SHIFT) # define OCOTP_LOCK_FIELD_RETURN(n) ((uint32_t)(n) << OCOTP_LOCK_FIELD_RETURN_SHIFT) +#endif /* CONFIG_ARCH_FAMILY_IMXRT118x */ + #endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_OCOTP_H */ diff --git a/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_ocotp.h b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_ocotp.h new file mode 100644 index 00000000000..8ddd178799c --- /dev/null +++ b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_ocotp.h @@ -0,0 +1,47 @@ +/**************************************************************************** + * arch/arm/src/imxrt/hardware/rt118x/imxrt118x_ocotp.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_OCOTP_H +#define __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_OCOTP_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* On i.MX RT chips fronted by the EdgeLock Enclave (RT1180 and later), + * the OCOTP fuse controller is owned by the ELE (IMXRT1180RM Ch. 7.1.2). + * The SoC exposes a read-only window of the non-security-related OCOTP + * shadow registers at: + * + * IMXRT_OCOTP_SHADOW_BASE + 0x4 * <fuse word index> + * + * (IMXRT1180RM Ch. 26.1 "Fusemap"). + * + * Write and reload paths must go through the ELE messaging protocol. + * That is not implemented in this port; imxrt_ocotp_write() and + * imxrt_ocotp_reload() therefore return -ENOSYS on chips with + * CONFIG_IMXRT_ELE=y. + */ + +#define IMXRT_OCOTP_SHADOW_BASE (0x47518000ul) + +#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_OCOTP_H */ diff --git a/arch/arm/src/imxrt/imxrt_ocotp.c b/arch/arm/src/imxrt/imxrt_ocotp.c index cbb45ef7bd9..24ac4b716d9 100644 --- a/arch/arm/src/imxrt/imxrt_ocotp.c +++ b/arch/arm/src/imxrt/imxrt_ocotp.c @@ -49,6 +49,15 @@ * Private Function ****************************************************************************/ +#ifndef CONFIG_ARCH_FAMILY_IMXRT118x + +/* The private helpers below drive the classic OCOTP MMIO register + * controller present on RT10xx / RT117x. On chips that ship an EdgeLock + * Enclave (RT1180 / CONFIG_ARCH_FAMILY_IMXRT118x=y) the fuse controller + * is owned by the ELE and the SoC only exposes a shadow-read window; + * those chips do not need or have these helpers. + */ + static inline void imxrt_ocotp_reset_errors(void) { putreg32(OCOTP_CTRL_ERROR, IMXRT_OCOTP_CTRL_CLR); @@ -187,6 +196,8 @@ static int imxrt_ocotp_wait_for_completion(uint32_t timeout_ms) return OK; } +#endif /* !CONFIG_ARCH_FAMILY_IMXRT118x */ + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -199,8 +210,16 @@ static int imxrt_ocotp_wait_for_completion(uint32_t timeout_ms) * ****************************************************************************/ -int imxrt_ocotp_reload() +int imxrt_ocotp_reload(void) { +#ifdef CONFIG_ARCH_FAMILY_IMXRT118x + /* Shadow reload on ELE-equipped chips (e.g. RT1180) is owned by the + * EdgeLock Enclave and would need to go through its messaging protocol. + * Not implemented in this port. + */ + + return -ENOSYS; +#else int ret; ret = imxrt_ocotp_wait_for_completion(OCOTP_OPT_TIMEOUT_MS); @@ -214,6 +233,7 @@ int imxrt_ocotp_reload() } return ret; +#endif } /**************************************************************************** @@ -234,6 +254,20 @@ int imxrt_ocotp_reload() int imxrt_ocotp_read(uint32_t otp_index, uint32_t *data) { +#ifdef CONFIG_ARCH_FAMILY_IMXRT118x + /* On ELE-equipped chips (e.g. RT1180) the SoC only exposes a read-only + * window of the non-security-related OCOTP shadow registers. Access it + * directly via IMXRT_OCOTP_SHADOW_BASE. + */ + + if (data == NULL) + { + return -EINVAL; + } + + *data = getreg32(IMXRT_OCOTP_SHADOW_BASE + (otp_index * 4)); + return OK; +#else int ret; ret = imxrt_ocotp_wait_for_completion(OCOTP_OPT_TIMEOUT_MS); @@ -262,6 +296,7 @@ int imxrt_ocotp_read(uint32_t otp_index, uint32_t *data) } return ret; +#endif } /**************************************************************************** @@ -283,6 +318,15 @@ int imxrt_ocotp_read(uint32_t otp_index, uint32_t *data) int imxrt_ocotp_write(uint32_t otp_index, uint32_t data) { +#ifdef CONFIG_ARCH_FAMILY_IMXRT118x + /* Fuse writes on ELE-equipped chips must go through the EdgeLock + * Enclave messaging protocol. Not implemented in this port. + */ + + UNUSED(otp_index); + UNUSED(data); + return -ENOSYS; +#else int ret; ret = imxrt_ocotp_wait_for_completion(OCOTP_OPT_TIMEOUT_MS); @@ -312,4 +356,5 @@ int imxrt_ocotp_write(uint32_t otp_index, uint32_t data) } return ret; +#endif }
