This is an automated email from the ASF dual-hosted git repository. xiaoxiang781216 pushed a commit to branch master in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit 62cc75c6910393136efaacb325b42b802fc218ed Author: Jukka Laitinen <[email protected]> AuthorDate: Mon Sep 28 16:08:04 2026 +0300 arch/arm/imxrt: Fix LPSPI frequency setting for imxrt1180 The LPSPI_CCR register is write only in imxrt1180. Therefore, the existing modifyreg32 calls can't be used to set the fields. Use direct putreg8 writes to update the PCSSCK, SCKPCS, DBT and SCKDIV. Signed-off-by: Jukka Laitinen <[email protected]> --- arch/arm/src/imxrt/hardware/imxrt_lpspi.h | 4 ++++ arch/arm/src/imxrt/imxrt_lpspi.c | 20 ++++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/arch/arm/src/imxrt/hardware/imxrt_lpspi.h b/arch/arm/src/imxrt/hardware/imxrt_lpspi.h index 6585316a996..11ff130c273 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_lpspi.h +++ b/arch/arm/src/imxrt/hardware/imxrt_lpspi.h @@ -47,6 +47,10 @@ #define IMXRT_LPSPI_DMR0_OFFSET 0x0030 /* Data Match Register 0 offset */ #define IMXRT_LPSPI_DMR1_OFFSET 0x0034 /* Data Match Register 1 offset */ #define IMXRT_LPSPI_CCR_OFFSET 0x0040 /* Clock Configuration Register offset */ +#define IMXRT_LPSPI_CCR_SCKDIV_OFFSET 0x0040 /* SCK divider byte offset */ +#define IMXRT_LPSPI_CCR_DBT_OFFSET 0x0041 /* Delay between transfers byte offset */ +#define IMXRT_LPSPI_CCR_PCSSCK_OFFSET 0x0042 /* PCS-to-SCK delay byte offset */ +#define IMXRT_LPSPI_CCR_SCKPCS_OFFSET 0x0043 /* SCK-to-PCS delay byte offset */ #define IMXRT_LPSPI_FCR_OFFSET 0x0058 /* FIFO Control Register offset */ #define IMXRT_LPSPI_FSR_OFFSET 0x005C /* FIFO Status Register offset */ #define IMXRT_LPSPI_TCR_OFFSET 0x0060 /* Transmit Command Register offset */ diff --git a/arch/arm/src/imxrt/imxrt_lpspi.c b/arch/arm/src/imxrt/imxrt_lpspi.c index 087582ae040..4ffb7050f66 100644 --- a/arch/arm/src/imxrt/imxrt_lpspi.c +++ b/arch/arm/src/imxrt/imxrt_lpspi.c @@ -684,28 +684,43 @@ static inline void imxrt_lpspi_master_set_delay_scaler( { case LPSPI_PCS_TO_SCK: { +#ifdef CONFIG_ARCH_FAMILY_IMXRT118x + putreg8((uint8_t)scaler, + priv->spibase + IMXRT_LPSPI_CCR_PCSSCK_OFFSET); +#else imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET, LPSPI_CCR_PCSSCK_MASK, 0); imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET, 0, LPSPI_CCR_PCSSCK(scaler)); +#endif break; } case LPSPI_LAST_SCK_TO_PCS: { +#ifdef CONFIG_ARCH_FAMILY_IMXRT118x + putreg8((uint8_t)scaler, + priv->spibase + IMXRT_LPSPI_CCR_SCKPCS_OFFSET); +#else imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET, LPSPI_CCR_SCKPCS_MASK, 0); imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET, 0, LPSPI_CCR_SCKPCS(scaler)); +#endif break; } case LPSPI_BETWEEN_TRANSFER: { +#ifdef CONFIG_ARCH_FAMILY_IMXRT118x + putreg8((uint8_t)scaler, + priv->spibase + IMXRT_LPSPI_CCR_DBT_OFFSET); +#else imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET, LPSPI_CCR_DBT_MASK, 0); imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET, 0, LPSPI_CCR_DBT(scaler)); +#endif break; } } @@ -1064,9 +1079,14 @@ static uint32_t imxrt_lpspi_setfrequency(struct spi_dev_s *dev, /* Write the best values in the CCR register */ +#ifdef CONFIG_ARCH_FAMILY_IMXRT118x + putreg8((uint8_t)best_scaler, + priv->spibase + IMXRT_LPSPI_CCR_SCKDIV_OFFSET); +#else imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CCR_OFFSET, LPSPI_CCR_SCKDIV_MASK, LPSPI_CCR_SCKDIV(best_scaler)); +#endif imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_TCR_OFFSET, LPSPI_TCR_PRESCALE_MASK,
