acassis commented on code in PR #8055: URL: https://github.com/apache/nuttx/pull/8055#discussion_r1064043584
########## arch/arm/src/stm32wb/stm32wb_i2c.c: ########## @@ -0,0 +1,2650 @@ +/**************************************************************************** + * arch/arm/src/stm32wb/stm32wb_i2c.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* -------------------------------------------------------------------------- + * + * STM32 WB I2C Driver based on L4 I2C Driver: + * + * STM32 WB and L4 have identical I2C hardware, differences are only in + * clocking. + * + * Supports: + * - Master operation: + * Standard-mode (up to 100 kHz) + * Fast-mode (up to 400 kHz) + * Fast-mode+ (up to 1 MHz) + * Clock source selection is based on STM32WB_RCC_CCIPR register + * + * - Multiple instances (shared bus) + * - Interrupt based operation + * - RELOAD support + * - I2C_M_NOSTART support + * + * Test Environment: + * - STM32WB55RG based board + * + * Unsupported, possible future work: + * - Wakeup from Stop mode + * - More effective error reporting to higher layers + * - Slave operation + * - Support of clock source frequencies other than 64MHz + * - Polled operation (code present but untested) + * - SMBus support + * - Multi-master support + * - IPMI + * + * Implementation: + * + * - Device: structure as defined by the nuttx/i2c/i2c_master.h + * + * - Instance: represents each individual access to the I2C driver, obtained + * by the i2c_init(); it extends the Device structure from the + * nuttx/i2c/i2c_master.h; + * Instance points to OPS, to common I2C Hardware private data and + * contains its own private data including frequency, address and mode + * of operation. + * + * - Private: Private data of an I2C Hardware + * + * High Level Functional Description + * + * This driver works with I2C "messages" (struct i2c_msg_s), which carry a + * buffer intended to transfer data to, or store data read from, the I2C bus. + * + * As the hardware can only transmit or receive one byte at a time the basic + * job of the driver (and the ISR specifically) is to process each message in + * the order they are stored in the message list, one byte at a time. When + * no messages are left the ISR exits and returns the result to the caller. + * + * The order of the list of I2C messages provided to the driver is important + * and dependent upon the hardware in use. A typical I2C transaction between + * the F3 as an I2C Master and some other IC as a I2C Slave requires two + * messages that communicate the: + * + * 1) Subaddress (register offset on the slave device) + * 2) Data sent to or read from the device + * + * These messages will typically be one byte in length but may be up to 2^31 + * bytes in length. Incidentally, the maximum length is limited only because + * i2c_msg_s.length is a signed int for some odd reason. + * + * Interrupt mode relies on the following interrupt events: + * + * TXIS - Transmit interrupt + * (data transmitted to bus and acknowledged) + * NACKF - Not Acknowledge Received + * (data transmitted to bus and NOT acknowledged) + * RXNE - Receive interrupt + * (data received from bus) + * TC - Transfer Complete + * (All bytes in message transferred) + * TCR - Transfer Complete (Reload) + * (Current batch of bytes in message transferred) + * + * The driver currently supports Single Master mode only. Slave mode is not + * supported. Additionally, the driver runs in Software End Mode (AUTOEND + * disabled) so the driver is responsible for telling the hardware what to + * do at the end of a transfer. + * + * -------------------------------------------------------------------------- + * + * Configuration: + * + * To use this driver, enable the following configuration variable: + * + * CONFIG_STM32WB_I2C + * + * and one or more interfaces: + * + * CONFIG_STM32WB_I2C1 + * CONFIG_STM32WB_I2C3 + * + * To configure the ISR timeout using fixed values + * (CONFIG_STM32WB_I2C_DYNTIMEO=n): + * + * CONFIG_STM32WB_I2CTIMEOSEC (Timeout in seconds) + * CONFIG_STM32WB_I2CTIMEOMS (Timeout in milliseconds) + * CONFIG_STM32WB_I2CTIMEOTICKS (Timeout in ticks) + * + * To configure the ISR timeout using dynamic values + * (CONFIG_STM32WB_I2C_DYNTIMEO=y): + * + * CONFIG_STM32WB_I2C_DYNTIMEO_USECPERBYTE + * (Timeout in microseconds per byte) + * CONFIG_STM32WB_I2C_DYNTIMEO_STARTSTOP + * (Timeout for start/stop in milliseconds) + * + * Debugging output enabled with: + * + * CONFIG_DEBUG_FEATURES and CONFIG_DEBUG_I2C_{ERROR|WARN|INFO} + * + * ISR Debugging output may be enabled with: + * + * CONFIG_DEBUG_FEATURES and CONFIG_DEBUG_I2C_INFO + * + * -------------------------------------------------------------------------- + * + * References (STM32WB): + * + * RM0434: + * ST STM32WB55xx and STM32WB35xx Reference Manual + * + * RM0471: + * ST STM32WB50CG and STM32WB30CE Reference Manual + * + * -------------------------------------------------------------------------- + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <sys/types.h> +#include <inttypes.h> +#include <stdio.h> +#include <stdlib.h> +#include <stdint.h> +#include <stdbool.h> +#include <stddef.h> +#include <assert.h> +#include <errno.h> +#include <debug.h> + +#include <nuttx/arch.h> +#include <nuttx/irq.h> +#include <nuttx/clock.h> +#include <nuttx/mutex.h> +#include <nuttx/semaphore.h> +#include <nuttx/kmalloc.h> +#include <nuttx/power/pm.h> +#include <nuttx/i2c/i2c_master.h> + +#include <arch/board/board.h> + +#include "arm_internal.h" +#include "stm32wb_gpio.h" +#include "stm32wb_rcc.h" +#include "stm32wb_i2c.h" +#include "stm32wb_waste.h" + +/* At least one I2C peripheral must be enabled */ + +#if defined(CONFIG_STM32WB_I2C1) || defined(CONFIG_STM32WB_I2C3) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* CONFIG_I2C_POLLED may be set so that I2C interrupts will not be used. + * Instead, CPU-intensive polling will be used. + */ + +/* Interrupt wait timeout in seconds and milliseconds */ + +#if !defined(CONFIG_STM32WB_I2CTIMEOSEC) && !defined(CONFIG_STM32WB_I2CTIMEOMS) +# define CONFIG_STM32WB_I2CTIMEOSEC 0 +# define CONFIG_STM32WB_I2CTIMEOMS 500 /* Default is 500 milliseconds */ +# warning "Using Default 500 Ms Timeout" +#elif !defined(CONFIG_STM32WB_I2CTIMEOSEC) +# define CONFIG_STM32WB_I2CTIMEOSEC 0 /* User provided milliseconds */ +#elif !defined(CONFIG_STM32WB_I2CTIMEOMS) +# define CONFIG_STM32WB_I2CTIMEOMS 0 /* User provided seconds */ +#endif + +/* Interrupt wait time timeout in system timer ticks */ + +#ifndef CONFIG_STM32WB_I2CTIMEOTICKS +# define CONFIG_STM32WB_I2CTIMEOTICKS \ + (SEC2TICK(CONFIG_STM32WB_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32WB_I2CTIMEOMS)) +#endif + +#ifndef CONFIG_STM32WB_I2C_DYNTIMEO_STARTSTOP +# define CONFIG_STM32WB_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32WB_I2CTIMEOTICKS) +#endif + +/* Macros to convert a I2C pin to a GPIO output */ Review Comment: ```suggestion /* Macros to convert an I2C pin to a GPIO output */ ########## arch/arm/src/stm32wb/stm32wb_i2c.c: ########## @@ -0,0 +1,2650 @@ +/**************************************************************************** + * arch/arm/src/stm32wb/stm32wb_i2c.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* -------------------------------------------------------------------------- + * + * STM32 WB I2C Driver based on L4 I2C Driver: + * + * STM32 WB and L4 have identical I2C hardware, differences are only in + * clocking. + * + * Supports: + * - Master operation: + * Standard-mode (up to 100 kHz) + * Fast-mode (up to 400 kHz) + * Fast-mode+ (up to 1 MHz) + * Clock source selection is based on STM32WB_RCC_CCIPR register + * + * - Multiple instances (shared bus) + * - Interrupt based operation + * - RELOAD support + * - I2C_M_NOSTART support + * + * Test Environment: + * - STM32WB55RG based board + * + * Unsupported, possible future work: + * - Wakeup from Stop mode + * - More effective error reporting to higher layers + * - Slave operation + * - Support of clock source frequencies other than 64MHz + * - Polled operation (code present but untested) + * - SMBus support + * - Multi-master support + * - IPMI + * + * Implementation: + * + * - Device: structure as defined by the nuttx/i2c/i2c_master.h + * + * - Instance: represents each individual access to the I2C driver, obtained + * by the i2c_init(); it extends the Device structure from the + * nuttx/i2c/i2c_master.h; + * Instance points to OPS, to common I2C Hardware private data and + * contains its own private data including frequency, address and mode + * of operation. + * + * - Private: Private data of an I2C Hardware + * + * High Level Functional Description + * + * This driver works with I2C "messages" (struct i2c_msg_s), which carry a + * buffer intended to transfer data to, or store data read from, the I2C bus. + * + * As the hardware can only transmit or receive one byte at a time the basic + * job of the driver (and the ISR specifically) is to process each message in + * the order they are stored in the message list, one byte at a time. When + * no messages are left the ISR exits and returns the result to the caller. + * + * The order of the list of I2C messages provided to the driver is important + * and dependent upon the hardware in use. A typical I2C transaction between + * the F3 as an I2C Master and some other IC as a I2C Slave requires two Review Comment: What is F3? Is it some residual reference to STM32F3 ? -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
