liangfu commented on issue #4986: [VTA][Chisel,de10nano] Chisel fixes and de10nano support URL: https://github.com/apache/incubator-tvm/pull/4986#issuecomment-594992227 > This makes me realize that we may want to run CI testing for different FPGA parameterizations in TSIM, e.g. DE10Nano, Pynq, F1. This might consume quite a bit of compute cycles, so they would just be done on unit tests. Agree, as long as we preserve at least one TSIM based integration test in the CI.
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