Aristide021 opened a new pull request, #18247: URL: https://github.com/apache/tvm/pull/18247
This commit introduces a vendor-neutral NPU backend that demonstrates architectural patterns common across Neural Processing Units. The implementation covers key NPU concepts including multi-tier memory hierarchy management, automatic tiling for large tensors, quantization handling, and specialized execution engines. It shows how NPUs manage memory across different tiers (L0/L1/L2/L3), tile operations to fit in on-chip SRAM, and dispatch operations to dedicated compute units. This serves as an educational template for developers creating NPU backends, demonstrating BYOC integration while teaching NPU-specific optimization strategies. Uses CPU emulation for testing without requiring actual NPU hardware. CC @tqchen - This addresses your feedback from #18201 regarding generic NPU BYOC tutorials. -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
