This is an automated email from the ASF dual-hosted git repository. areusch pushed a change to branch add-riscv-image in repository https://gitbox.apache.org/repos/asf/tvm.git
discard 84d92dae6c Add ci_riscv image, update all to 20220810-060142-fae79bbc3. add 3eb673478b [LowerVTCMAlloc] Move LowerVtcmAlloc to after StorageRewrite (#12364) add 57a02f7e26 Update hexagon max_concurrency to be at most equal to the number of HVX units available. (#12394) add 478b672f2b [skip ci] Revert "[ci] Default to n=2 for test parallelism (#12376)" (#12413) add 1737308397 [WIP][Pylint] Making frontend tests pylint compliant (#12028) add 96cac7501d [MetaSchedule] Filter vector_load_lens based on buffer dtype (#12408) add 036aa722ae [TIR] Add pass ManifestSharedMemoryLocalStage (#12355) add d33a332283 [TVMScript] Printer VarTable (#12336) add 8dd621e564 [TIR] Expose ScriptComplete in header (#12419) add d8846ec975 [TOPI][OP]change float multiplication of resize op to integer division (#12315) add 33bf708755 [Fix] Fix precision issue in FFI converting `int/float` to `PrimExpr` (#12417) add 0ac5dd7f64 [Fix] Fix errors in error checking and reporting (#12423) add 24d9d398bb Add `operator()` to `support::With` (#12418) add 8ec7a0a460 [TIR] Fix assert for tensorcore int8 intrinsics (#12365) add 9d4df89833 [TIR] Allow converting `BufferRegion` to vectorized `BufferLoad` (#12420) add 57a3b26343 [Fix] Fix `dtype` in Cache-Read/Write (#12421) add e3d0305881 [TIR] Avoid `import *` in TIR tensor intrinsic registration (#12424) add e111984117 [TIR] Allow `tir.Buffer` converted to `BufferLoad/BufferRegion` with `__getitem__` (#12422) add d805ae3bd9 [TIR] Expose: `call_packed_lowered`, `call_cpacked_lowered` (#12425) add bb513866ad [TIR] Expose Stack-related TVM builtins in Python (#12429) add 849b2f9709 [CI][AArch64] Enable ONNX installation in ci_arm image (#12438) add 25c4a73b1d Add ci_riscv image, update all to 20220810-060142-fae79bbc3. (#12369) add 55f1d7e2c4 [TIR][UX] allow override when register TensorIntrin (#12439) add 03d43e3e8b Add RISC-V build/test pipeline to Jenkins. This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (84d92dae6c) \ N -- N -- N refs/heads/add-riscv-image (03d43e3e8b) You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omit" are not gone; other references still refer to them. Any revisions marked "discard" are gone forever. No new revisions were added by this update. Summary of changes: Jenkinsfile | 312 ++++--- ci/jenkins/Build.groovy.j2 | 18 + ci/jenkins/Jenkinsfile.j2 | 2 +- ci/jenkins/Test.groovy.j2 | 17 + ci/jenkins/generate.py | 10 +- ci/jenkins/macros.j2 | 3 - docker/Dockerfile.ci_arm | 4 + include/tvm/ir/expr.h | 4 +- include/tvm/script/printer/var_table.h | 144 +++ include/tvm/support/with.h | 2 + include/tvm/tir/function.h | 3 +- include/tvm/tir/stmt.h | 3 + include/tvm/tir/transform.h | 6 + python/tvm/meta_schedule/default_config.py | 6 +- python/tvm/meta_schedule/testing/schedule_rule.py | 10 +- python/tvm/script/printer/var_table.py | 118 +++ python/tvm/script/tir/scope_handler.py | 4 +- python/tvm/te/operation.py | 14 +- python/tvm/tir/__init__.py | 2 + python/tvm/tir/buffer.py | 41 +- python/tvm/tir/function.py | 10 +- python/tvm/tir/op.py | 123 +++ python/tvm/tir/tensor_intrin/__init__.py | 6 +- python/tvm/tir/tensor_intrin/arm_cpu.py | 1 + python/tvm/tir/tensor_intrin/cuda.py | 4 +- python/tvm/tir/transform/transform.py | 11 + python/tvm/topi/image/resize.py | 65 +- src/driver/driver_api.cc | 4 +- src/ir/expr.cc | 15 + .../schedule_rule/multi_level_tiling.cc | 29 +- src/runtime/threading_backend.cc | 20 +- src/script/printer/var_table.cc | 108 +++ src/tir/ir/expr.cc | 18 +- src/tir/ir/function.cc | 8 +- src/tir/ir/script/script_complete.cc | 5 +- .../vision.cc => tir/ir/script/script_complete.h} | 22 +- src/tir/schedule/primitive/cache_read_write.cc | 2 +- .../manifest_shared_memory_local_stage.cc | 287 ++++++ src/tir/transforms/storage_rewrite.cc | 6 +- tests/cpp/tvmscript_printer_var_table_test.cc | 158 ++++ tests/lint/pylint.sh | 13 + tests/python/frontend/caffe/test_forward.py | 79 +- tests/python/frontend/caffe2/model_zoo/__init__.py | 2 +- .../python/frontend/caffe2/model_zoo/squeezenet.py | 10 +- tests/python/frontend/caffe2/test_forward.py | 26 +- tests/python/frontend/coreml/model_zoo/__init__.py | 8 +- tests/python/frontend/coreml/test_forward.py | 194 ++-- tests/python/frontend/darknet/test_forward.py | 37 +- tests/python/frontend/keras/test_forward.py | 743 ++++++++-------- tests/python/frontend/oneflow/test_forward.py | 67 +- .../python/frontend/oneflow/test_vision_models.py | 10 +- tests/python/frontend/onnx/test_forward.py | 985 ++++++++++++--------- tests/python/frontend/pytorch/test_forward.py | 467 +++++++--- tests/python/frontend/tensorflow/test_forward.py | 328 ++++--- tests/python/frontend/tflite/test_forward.py | 384 ++++---- .../test_meta_schedule_auto_tensorize.py | 9 +- tests/python/topi/python/test_topi_image.py | 3 + tests/python/topi/python/test_topi_upsampling.py | 41 + ...est_meta_schedule_postproc_rewrite_tensorize.py | 2 +- ...ta_schedule_schedule_rule_multi_level_tiling.py | 20 +- .../unittest/test_meta_schedule_tune_relay.py | 8 +- tests/python/unittest/test_target_codegen_llvm.py | 15 +- .../python/unittest/test_tir_schedule_tensorize.py | 11 +- ...transform_manifest_shared_memory_local_stage.py | 134 +++ .../unittest/test_tvmscript_printer_var_table.py | 89 ++ tests/scripts/setup-pytest-env.sh | 8 +- ...egration_i386only.sh => task_riscv_microtvm.sh} | 6 +- 67 files changed, 3723 insertions(+), 1601 deletions(-) create mode 100644 include/tvm/script/printer/var_table.h create mode 100644 python/tvm/script/printer/var_table.py create mode 100644 src/script/printer/var_table.cc copy src/{topi/vision.cc => tir/ir/script/script_complete.h} (67%) create mode 100644 src/tir/transforms/manifest_shared_memory_local_stage.cc create mode 100644 tests/cpp/tvmscript_printer_var_table_test.cc create mode 100644 tests/python/unittest/test_tir_transform_manifest_shared_memory_local_stage.py create mode 100644 tests/python/unittest/test_tvmscript_printer_var_table.py copy tests/scripts/{task_python_integration_i386only.sh => task_riscv_microtvm.sh} (89%) mode change 100755 => 100644