On Fri, 10 Apr 2026 22:42:34 GMT, Sandhya Viswanathan
<[email protected]> wrote:
>> Jatin Bhateja has updated the pull request incrementally with one additional
>> commit since the last revision:
>>
>> Review comments resolution
>
> src/hotspot/cpu/x86/assembler_x86.cpp line 6779:
>
>> 6777: void Assembler::vpalignr(XMMRegister dst, XMMRegister nds, XMMRegister
>> src, int imm8, int vector_len) {
>> 6778: assert(UseAVX > 0 && (vector_len == Assembler::AVX_512bit ||
>> (!needs_evex(dst, nds, src) || VM_Version::supports_avx512vl())), "");
>> 6779: assert(!needs_evex(dst, nds, src) ||
>> VM_Version::supports_avx512bw(), "");
>
> The AVX2 check for 256 bit should be retained.
>
> assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
> vector_len == AVX_256bit? VM_Version::supports_avx2() :
> vector_len == AVX_512bit? VM_Version::supports_avx512bw(), "");
>
>
> The higher bank xmm usage for < 512 bit vl is already covered by the
> _legacy_mode_bw in the attributes. The asserts in
> Assembler::vex_prefix_and_encode() check for xmm registers to be 0-15 in such
> case.
Slice from 256 bit floating points vector is valid at UseAVX=1, thus check
vector_len == AVX_256bit mandating AVX2 will result into assertion failure.
-------------
PR Review Comment: https://git.openjdk.org/jdk/pull/24104#discussion_r3077886915
