On Mon, 2008-01-21 at 00:24 +0100, Ronald Hoogenboom wrote:
> (LPC is the only datapath to the SB and CPU, so it has to!). We could
> optimize by omitting the wait for SPI ready when there is no data to be
> read, eg. readcnt==0. I'll have a look at what can be gained by that.
>
Omitting it saves 10 seconds with the unconditional 10us delay, reducing
to 40~45 secs. So I think it is worth putting it in. With the
conditional delay, it is not so easily measurable, because of the
natural variance much larger than 10 us...
Patch follows...
Signed-off-by: Ronald Hoogenboom <[EMAIL PROTECTED]>
---
Index: spi.c
===================================================================
--- spi.c (revision 3066)
+++ spi.c (working copy)
@@ -227,12 +227,14 @@
* We can't use writecnt directly, but have to use a strange encoding.
*/
outb(((0x4 + (fast_spi ? 1 : 0)) << 4) | ((readcnt & 0x3) << 2) | (writeenc), port);
- do {
- busy = inb(port) & 0x80;
- } while (busy);
-
- for (i = 0; i < readcnt; i++) {
- readarr[i] = inb(port + 5 + i);
+ if (readcnt > 0) {
+ do {
+ busy = inb(port) & 0x80;
+ } while (busy);
+ i=0;
+ do {
+ readarr[i] = inb(port + 5 + i);
+ } while (++i < readcnt);
}
return 0;
--
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