Stefan Reinauer <[EMAIL PROTECTED]> writes:
>> I have thought about this a while back and have wanted to make a
>> change. Disabling CAR should fixup the stack etc but for performance
>> reasons we should setup/leave ROM and RAM caching enabled on the BSP.
>> If you are interested in looking at that I think it would be great.
>
> What CPU/chipset is this? On quite some ROM stays cacheable all the
> time, afaik
I've seen this performance issue on my Tyan test rig; s2912 mainboard,
mcp55 southbridge and 83xx Opterons. From the code in the
serengeti_cheetah_fam10 target I'd expect the same behavior to manifest
there.
--
Arne.
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