Hi Harald, I fixed some stuff and made a new build. * now my NIC MAC address is same as factory (in romstrap.inc): no 'renaming' anymore. * now the FACP checksum is correct (new fadt.c attached) * powernow still doesn't work (enabled the commented acpi_fill_ssdt_generator in acpi.c, but doesn't help...)
New artefact: ACPI Error (evgpeblk-1156): GPE0 block (GPE 0 to 31) overlaps the GPE1 block (GPE 20 to 59) - Ignoring GPE1 [20070126] Continued artefacts: ACPI Exception (processor_core-0818): AE_NOT_FOUND, Processor Device is not present [20070126] (2 times) powernow-k8: MP systems not supported by PSB BIOS structure (2 times) On Wed, 2009-05-27 at 20:54 +0200, Harald Gutmann wrote: > PS: I think it would be better to keep this discussion on the mailing list, > so > everyone can post his hints/opinions/suggestions to that topic. > Mailing list is copied too... Best regards, Ronald.
/* * This file is part of the coreboot project. * * Copyright (C) 2004 Nick Barker <[email protected]> * Copyright (C) 2007 Rudolf Marek <[email protected]> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <console/console.h> #include <string.h> #include <arch/acpi.h> #include <arch/io.h> #include <../../../southbridge/nvidia/mcp55/chip.h> #include <../../../southbridge/nvidia/mcp55/mcp55_early_setup_ss.h> #include <../../../southbridge/nvidia/mcp55/mcp55_smbus.h> extern unsigned pm_base; /** * Create the Fixed ACPI Description Tables (FADT) for this board. */ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) { acpi_header_t *header = &(fadt->header); memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); header->revision = 1; memcpy(header->oem_id, "GBT", 6); memcpy(header->oem_table_id, "NVDAACPI ", 8); memcpy(header->asl_compiler_id, "NVDA", 4); header->asl_compiler_revision = 0; printk_info("ACPI: pm_base: %u...\n", pm_base); fadt->firmware_ctrl = facs; fadt->dsdt = dsdt; fadt->preferred_pm_profile = 1; fadt->sci_int = 9; fadt->smi_cmd = 0x142e; fadt->acpi_enable = 0xa1; fadt->acpi_disable = 0xa0; fadt->s4bios_req = 0x0; fadt->pstate_cnt = 0x0; fadt->pm1a_evt_blk = pm_base; fadt->pm1b_evt_blk = 0x1; fadt->pm1a_cnt_blk = pm_base + 0x4; fadt->pm1b_cnt_blk = 0x0; fadt->pm2_cnt_blk = pm_base + 0x1c; fadt->pm_tmr_blk = pm_base + 0x8; fadt->gpe0_blk = pm_base + 0x20; fadt->gpe1_blk = pm_base + 0x4a0; fadt->pm1_evt_len = 4; fadt->pm1_cnt_len = 2; fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 8; fadt->gpe1_blk_len = 10; fadt->gpe1_base = 20; fadt->cst_cnt = 0; fadt->p_lvl2_lat = 0x65; fadt->p_lvl3_lat = 0x3e9; fadt->flush_size = 0; fadt->flush_stride = 0; fadt->duty_offset = 1; fadt->duty_width = 3; fadt->day_alrm = 0x7d; fadt->mon_alrm = 0x7e; fadt->century = 0x32; fadt->iapc_boot_arch = 0x1; fadt->flags = 0x4a5; fadt->reset_reg.space_id = 0; fadt->reset_reg.bit_width = 0; fadt->reset_reg.bit_offset = 0; fadt->reset_reg.resv = 0; fadt->reset_reg.addrl = 0x0; fadt->reset_reg.addrh = 0x0; fadt->reset_value = 0; fadt->x_firmware_ctl_l = facs; fadt->x_firmware_ctl_h = 0; fadt->x_dsdt_l = dsdt; fadt->x_dsdt_h = 0; fadt->x_pm1a_evt_blk.space_id = 1; fadt->x_pm1a_evt_blk.bit_width = 4; fadt->x_pm1a_evt_blk.bit_offset = 0; fadt->x_pm1a_evt_blk.resv = 0; fadt->x_pm1a_evt_blk.addrl = pm_base; fadt->x_pm1a_evt_blk.addrh = 0x0; fadt->x_pm1b_evt_blk.space_id = 1; fadt->x_pm1b_evt_blk.bit_width = 4; fadt->x_pm1b_evt_blk.bit_offset = 0; fadt->x_pm1b_evt_blk.resv = 0; fadt->x_pm1b_evt_blk.addrl = 0x0; fadt->x_pm1b_evt_blk.addrh = 0x0; fadt->x_pm1a_cnt_blk.space_id = 1; fadt->x_pm1a_cnt_blk.bit_width = 2; fadt->x_pm1a_cnt_blk.bit_offset = 0; fadt->x_pm1a_cnt_blk.resv = 0; fadt->x_pm1a_cnt_blk.addrl = pm_base + 0x4; fadt->x_pm1a_cnt_blk.addrh = 0x0; fadt->x_pm1b_cnt_blk.space_id = 1; fadt->x_pm1b_cnt_blk.bit_width = 2; fadt->x_pm1b_cnt_blk.bit_offset = 0; fadt->x_pm1b_cnt_blk.resv = 0; fadt->x_pm1b_cnt_blk.addrl = 0x0; fadt->x_pm1b_cnt_blk.addrh = 0x0; fadt->x_pm2_cnt_blk.space_id = 1; fadt->x_pm2_cnt_blk.bit_width = 0; fadt->x_pm2_cnt_blk.bit_offset = 0; fadt->x_pm2_cnt_blk.resv = 0; fadt->x_pm2_cnt_blk.addrl = pm_base + 0x1c; fadt->x_pm2_cnt_blk.addrh = 0x0; fadt->x_pm_tmr_blk.space_id = 1; fadt->x_pm_tmr_blk.bit_width = 4; fadt->x_pm_tmr_blk.bit_offset = 0; fadt->x_pm_tmr_blk.resv = 0; fadt->x_pm_tmr_blk.addrl = pm_base + 0x8; fadt->x_pm_tmr_blk.addrh = 0x0; fadt->x_gpe0_blk.space_id = 1; fadt->x_gpe0_blk.bit_width = 0; fadt->x_gpe0_blk.bit_offset = 0; fadt->x_gpe0_blk.resv = 0; fadt->x_gpe0_blk.addrl = pm_base + 0x20; fadt->x_gpe0_blk.addrh = 0x0; fadt->x_gpe1_blk.space_id = 1; fadt->x_gpe1_blk.bit_width = 0; fadt->x_gpe1_blk.bit_offset = 0; fadt->x_gpe1_blk.resv = 0; fadt->x_gpe1_blk.addrl = pm_base + 0x4a0; fadt->x_gpe1_blk.addrh = 0x0; header->checksum = acpi_checksum((void *) fadt, header->length); }
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