Hi Stefan,
After trying all VSA`s i could find on the net back in
last December, no one was working.
So i hacked up my own.
Attached a log from rev5470.
Thanks,Nils.
coreboot-4.0-r5470M-V5470_142 Mon May 3 23:59:12 CEST 2010 starting...
POST: 0xa0
POST: 0xa1
coreboot-4.0-r5470M-V5470_142 Mon May 3 23:59:12 CEST 2010 starting...
done cpuRegInit
Ram1.00
Ram2.00
computed msr.hi 10077113
Ram3
RAM DLL lock
Ram4
ram setup done
CPU_RCONF_DEFAULT msr.hi 24fffc02
CPU_RCONF_DEFAULT msr.lo 1000a000
MSR_GLIU0_BASE1 msr.hi 20000000
MSR_GLIU0_BASE1 msr.lo 000fff80
MSR_GLIU0_BASE2 msr.hi 20000000
MSR_GLIU0_BASE2 msr.lo 080fffe0
MSR_GLIU0_SMM msr.hi 000000ff
MSR_GLIU0_SMM msr.lo fff00000
MSR_GLIU0_SYSMEM msr.hi 00000000
MSR_GLIU0_SYSMEM msr.lo 000fffff
MSR_GLIU0_SHADOW msr.hi 2000ffff
MSR_GLIU0_SHADOW msr.lo ffff0003
MSR_GLIU1_BASE1 msr.hi 20000000
MSR_GLIU1_BASE1 msr.lo 000fff80
MSR_GLIU1_BASE2 msr.hi 20000000
MSR_GLIU1_BASE2 msr.lo 080fffe0
MSR_GLIU1_SMM msr.hi 000000ff
MSR_GLIU1_SMM msr.lo fff00000
MSR_GLIU1_SYSMEM msr.hi 00000000
MSR_GLIU1_SYSMEM msr.lo 000fffff
MSR_GLIU1_SHADOW msr.hi 2000ffff
MSR_GLIU1_SHADOW msr.lo ffff0003
GLIU0_GLD_MSR_COH msr.hi 00000000
GLIU0_GLD_MSR_COH msr.lo 00000000
GLIU1_GLD_MSR_COH msr.hi 00000000
GLIU1_GLD_MSR_COH msr.lo 00000000
GLPCI_GLD_MSR_CONFIG msr.hi 00000000
GLPCI_GLD_MSR_CONFIG msr.lo 00000000
GLCP_GLD_MSR_CONF msr.hi 00000000
GLCP_GLD_MSR_CONF msr.lo 00000000
CPU_RCONF_A0_BF msr.hi 00000000
CPU_RCONF_A0_BF msr.lo 00000000
CPU_RCONF_C0_DF msr.hi 00000000
CPU_RCONF_C0_DF msr.lo 00000000
CPU_RCONF_E0_FF msr.hi 00000000
CPU_RCONF_E0_FF msr.lo 00000000
GLPCI_A0_BF msr.hi 00000000
GLPCI_A0_BF msr.lo 00000000
GLPCI_C0_DF msr.hi 00000000
GLPCI_C0_DF msr.lo 00000000
GLPCI_E0_FF msr.hi 00000000
GLPCI_E0_FF msr.lo 00000000
ram check done
Loading stage image.
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
Stage: loading fallback/coreboot_ram @ 0x4000 (131072 bytes), entry @ 0x4000
Stage: done loading.
Jumping to image.
POST: 0x80
POST: 0x39
coreboot-4.0-r5470M-V5470_142 Mon May 3 23:59:12 CEST 2010 booting...
POST: 0x40
clocks_per_usec: 366
Enumerating buses...
Show all devs...Before Device Enumeration.
Root Device: enabled 1, 0 resources
APIC_CLUSTER: 0: enabled 1, 0 resources
APIC: 00: enabled 1, 0 resources
PCI_DOMAIN: 0000: enabled 1, 0 resources
PCI: 00:01.0: enabled 1, 0 resources
PCI: 00:01.1: enabled 1, 0 resources
PCI: 00:0e.0: enabled 1, 0 resources
PCI: 00:0f.0: enabled 1, 0 resources
PCI: 00:0f.2: enabled 1, 0 resources
PCI: 00:0f.3: enabled 1, 0 resources
PCI: 00:0f.4: enabled 1, 0 resources
PCI: 00:0f.5: enabled 1, 0 resources
Compare with tree...
Root Device: enabled 1, 0 resources
APIC_CLUSTER: 0: enabled 1, 0 resources
APIC: 00: enabled 1, 0 resources
PCI_DOMAIN: 0000: enabled 1, 0 resources
PCI: 00:01.0: enabled 1, 0 resources
PCI: 00:01.1: enabled 1, 0 resources
PCI: 00:0e.0: enabled 1, 0 resources
PCI: 00:0f.0: enabled 1, 0 resources
PCI: 00:0f.2: enabled 1, 0 resources
PCI: 00:0f.3: enabled 1, 0 resources
PCI: 00:0f.4: enabled 1, 0 resources
PCI: 00:0f.5: enabled 1, 0 resources
scan_static_bus for Root Device
gx2 north: enable_dev
DEVICE_PATH_APIC_CLUSTER
gx2 north: end enable_dev
APIC_CLUSTER: 0 enabled
gx2 north: enable_dev
DEVICE_PATH_PCI_DOMAIN
Enter northbridgeinit
writeglmsr: write msr 0x10000020, val 0x20000000:0x000fff80
writeglmsr: AFTER write msr 0x10000020, val 0x20000000:0x000fff80
writeglmsr: write msr 0x10000021, val 0x20000000:0x080fffe0
writeglmsr: AFTER write msr 0x10000021, val 0x20000000:0x080fffe0
sizeram: 10077113:00003400
sizeram: sizem 0x200
SysmemInit: enable for 512m bytes
SysmemInit: AFTER write msr 0x10000028, val 0x2000001f:0xfdf00100
sizeram: 10077113:00003400
sizeram: sizem 0x200
sizeram: 10077113:00003400
sizeram: sizem 0x200
SMMGL0Init: 536739840 bytes
SMMGL0Init: offset is 0xdfbe0000
SMMGL0Init: AFTER write msr 0x10000026, val 0xfdfbe040:0x400fffe0
writeglmsr: write msr 0x10000080, val 0x00000000:0x00000003
writeglmsr: AFTER write msr 0x10000080, val 0x00000000:0x00000003
writeglmsr: write msr 0x40000020, val 0x20000000:0x000fff80
writeglmsr: AFTER write msr 0x40000020, val 0x20000000:0x000fff80
writeglmsr: write msr 0x40000021, val 0x20000000:0x080fffe0
writeglmsr: AFTER write msr 0x40000021, val 0x20000000:0x080fffe0
sizeram: 10077113:00003400
sizeram: sizem 0x200
SysmemInit: enable for 512m bytes
SysmemInit: AFTER write msr 0x40000029, val 0x2000001f:0xfdf00100
SMMGL1Init:
SMMGL1Init: AFTER write msr 0x40000023, val 0x20000040:0x400fffe0
writeglmsr: write msr 0x40000080, val 0x00000000:0x00000001
writeglmsr: AFTER write msr 0x40000080, val 0x00000000:0x00000001
writeglmsr: write msr 0x400000e3, val 0x60000000:0x033000f0
writeglmsr: AFTER write msr 0x400000e3, val 0x60000000:0x033000f0
GeodeLinkPriority: MSR 0x00002001 is 0x00000000:0x00000320
GeodeLinkPriority: MSR 0x00002001 will be set to 0x00000000:0x00000220
GeodeLinkPriority: MSR 0xc0002001 is 0x00000000:0x00040e80
GeodeLinkPriority: MSR 0xc0002001 will be set to 0x00000000:0x00040000
GeodeLinkPriority: MSR 0x80002001 is 0x00000000:0x00000000
GeodeLinkPriority: MSR 0x80002001 will be set to 0x00000000:0x00000720
GeodeLinkPriority: MSR 0xa0002001 is 0x00000000:0x00000000
GeodeLinkPriority: MSR 0xa0002001 will be set to 0x00000000:0x00000010
GeodeLinkPriority: MSR 0x50002001 is 0x00000000:0x00000000
GeodeLinkPriority: MSR 0x50002001 will be set to 0x00000000:0x00000027
GeodeLinkPriority: MSR 0x4c002001 is 0x00000000:0x00000000
GeodeLinkPriority: MSR 0x4c002001 will be set to 0x00000000:0x00000001
GeodeLinkPriority: MSR 0x54002001 is 0x00000000:0x00000000
GeodeLinkPriority: MSR 0x54002001 will be set to 0x00000000:0x00000622
GeodeLinkPriority: MSR 0x58002001 is 0x00000000:0x00000000
GeodeLinkPriority: MSR 0x58002001 will be set to 0x00000000:0x00000013
GLPCI r1: system msr.lo 0xfdf00100 msr.hi 0x2000001f
GLPCI r1: system msr.lo 0x00100130 msr.hi 0x1ffdf000
ClockGatingInit: MSR 0x10002004 is 0x00000000:0x00000000
ClockGatingInit: MSR 0x10002004 will be set to 0x00000000:0x00000005
ClockGatingInit: MSR 0x20002004 is 0x00000000:0x00000001
ClockGatingInit: MSR 0x20002004 will be set to 0x00000000:0x00000001
ClockGatingInit: MSR 0x40002004 is 0x00000000:0x00000000
ClockGatingInit: MSR 0x40002004 will be set to 0x00000000:0x00000005
ClockGatingInit: MSR 0x80002004 is 0x00000000:0x00000000
ClockGatingInit: MSR 0x80002004 will be set to 0x00000000:0x00000000
ClockGatingInit: MSR 0xa0002004 is 0x00000000:0x00000000
ClockGatingInit: MSR 0xa0002004 will be set to 0x00000000:0x00000001
ClockGatingInit: MSR 0xc0002004 is 0x00000000:0x00000000
ClockGatingInit: MSR 0xc0002004 will be set to 0x00000000:0x00000155
ClockGatingInit: MSR 0x4c002004 is 0x00000000:0x00000000
ClockGatingInit: MSR 0x4c002004 will be set to 0x00000000:0x00000015
ClockGatingInit: MSR 0x50002004 is 0x00000000:0x00000000
ClockGatingInit: MSR 0x50002004 will be set to 0x00000000:0x00000015
ClockGatingInit: MSR 0x54002004 is 0x00000000:0x00000000
ClockGatingInit: MSR 0x54002004 will be set to 0x00000000:0x00000000
CPU_RCONF_DEFAULT msr.hi 25fffc02
CPU_RCONF_DEFAULT msr.lo 11ffdf00
MSR_GLIU0_BASE1 msr.hi 20000000
MSR_GLIU0_BASE1 msr.lo 000fff80
MSR_GLIU0_BASE2 msr.hi 20000000
MSR_GLIU0_BASE2 msr.lo 080fffe0
MSR_GLIU0_SMM msr.hi fdfbe040
MSR_GLIU0_SMM msr.lo 400fffe0
MSR_GLIU0_SYSMEM msr.hi 2000001f
MSR_GLIU0_SYSMEM msr.lo fdf00100
MSR_GLIU0_SHADOW msr.hi 2000ffff
MSR_GLIU0_SHADOW msr.lo ffff0003
MSR_GLIU1_BASE1 msr.hi 20000000
MSR_GLIU1_BASE1 msr.lo 000fff80
MSR_GLIU1_BASE2 msr.hi 20000000
MSR_GLIU1_BASE2 msr.lo 080fffe0
MSR_GLIU1_SMM msr.hi 20000040
MSR_GLIU1_SMM msr.lo 400fffe0
MSR_GLIU1_SYSMEM msr.hi 2000001f
MSR_GLIU1_SYSMEM msr.lo fdf00100
MSR_GLIU1_SHADOW msr.hi 2000ffff
MSR_GLIU1_SHADOW msr.lo ffff0003
GLIU0_GLD_MSR_COH msr.hi 00000000
GLIU0_GLD_MSR_COH msr.lo 00000003
GLIU1_GLD_MSR_COH msr.hi 00000000
GLIU1_GLD_MSR_COH msr.lo 00000001
GLPCI_GLD_MSR_CONFIG msr.hi 00000000
GLPCI_GLD_MSR_CONFIG msr.lo 00000027
GLCP_GLD_MSR_CONF msr.hi 00000000
GLCP_GLD_MSR_CONF msr.lo 00000001
CPU_RCONF_A0_BF msr.hi 21212121
CPU_RCONF_A0_BF msr.lo 21212121
CPU_RCONF_C0_DF msr.hi 00000000
CPU_RCONF_C0_DF msr.lo 00000000
CPU_RCONF_E0_FF msr.hi 00000000
CPU_RCONF_E0_FF msr.lo 00000000
GLPCI_A0_BF msr.hi 35353535
GLPCI_A0_BF msr.lo 35353535
GLPCI_C0_DF msr.hi 35353535
GLPCI_C0_DF msr.lo 35353535
GLPCI_E0_FF msr.hi 35353535
GLPCI_E0_FF msr.lo 35353535
Exit northbridgeinit
Doing cpubug fixes for rev 0x21
CPU_BUG:eng2900
Done cpubug fixes
POST: 0xe0
Not Doing ChipsetFlashSetup()
sizeram: 10077113:00003400
sizeram: sizem 0x200
setup_gx2_cache: enable for 524288 KB
msr 0x00001808 will be set to 25fff002:11ffe000
MSR 0x10000026 is now 0x2dfbe040:0x400fffe0
do_vsmbios
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fff00000 + 38 + 79ee + align -> fff07a40
Check fallback/payload
CBFS: follow chain: fff07a40 + 38 + 11038 + align -> fff18ac0
Check vsa
Stage: loading vsa @ 0x60000 (57868 bytes), entry @ 0x60020
Stage: done loading.
buf[0x20] signature is b0:10:e6:80
Call real_mode_switch_call_vsm
do_vsmbios: VSA2 VR signature verified
Finding PCI configuration type.
PCI: Using configuration type 1
POST: 0x5f
sizeram: 10077113:00003400
sizeram: sizem 0x200
gx2 north: end enable_dev
PCI_DOMAIN: 0000 enabled
PCI_DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
POST: 0x24
gx2 north: enable_dev
gx2 north: end enable_dev
PCI: 00:01.0 [100b/0028] ops
PCI: 00:01.0 [100b/0028] enabled
gx2 north: enable_dev
gx2 north: end enable_dev
PCI: 00:01.1 [100b/0030] enabled
cs5536: southbridge_enable: dev is 00014788
PCI: 00:0e.0 [10ec/8139] enabled
cs5536: southbridge_enable: dev is 00014bcc
PCI: 00:0f.0 [1022/2090] bus ops
PCI: 00:0f.0 [1022/2090] enabled
cs5536: southbridge_enable: dev is 00015010
PCI: 00:0f.2 [1022/209a] ops
PCI: 00:0f.2 [1022/209a] enabled
cs5536: southbridge_enable: dev is 00015454
PCI: 00:0f.3 [1022/2093] enabled
cs5536: southbridge_enable: dev is 00015898
PCI: 00:0f.4 [1022/2094] enabled
cs5536: southbridge_enable: dev is 00015cdc
PCI: 00:0f.5 [1022/2095] enabled
malloc Enter, size 1092, free_mem_ptr 00020000
malloc 00020000
PCI: 00:0f.6 [1022/2096] enabled
malloc Enter, size 1092, free_mem_ptr 00020444
malloc 00020444
PCI: 00:0f.7 [1022/2097] enabled
POST: 0x25
scan_static_bus for PCI: 00:0f.0
scan_static_bus for PCI: 00:0f.0 done
PCI: pci_scan_bus returning with max=000
POST: 0x55
scan_static_bus for Root Device done
done
POST: 0x66
Setting up VGA for PCI: 00:01.1
Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
APIC_CLUSTER: 0 read_resources bus 0 link: 0
APIC: 00 missing read_resources
APIC_CLUSTER: 0 read_resources bus 0 link: 0 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0
PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
Root Device links 1 child on link 0 APIC_CLUSTER: 0
APIC_CLUSTER: 0 links 1 child on link 0 APIC: 00
APIC: 00 links 0 child on link 0 NULL
PCI_DOMAIN: 0000 links 1 child on link 0 PCI: 00:01.0
PCI_DOMAIN: 0000 resource base 0 size 1f7e0000 align 0 gran 0 limit 0 flags e0004200 index 0
PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
PCI: 00:01.0 links 0 child on link 0 NULL
PCI: 00:01.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 10
PCI: 00:01.1 links 0 child on link 0 NULL
PCI: 00:01.1 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 10
PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 14
PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 18
PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c
PCI: 00:0e.0 links 0 child on link 0 NULL
PCI: 00:0e.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
PCI: 00:0e.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 14
PCI: 00:0f.0 links 0 child on link 0 NULL
PCI: 00:0f.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
PCI: 00:0f.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 14
PCI: 00:0f.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 18
PCI: 00:0f.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 1c
PCI: 00:0f.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 20
PCI: 00:0f.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 24
PCI: 00:0f.0 resource base 0 size 400 align 0 gran 0 limit ffff flags c0000100 index 1
PCI: 00:0f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
PCI: 00:0f.2 links 0 child on link 0 NULL
PCI: 00:0f.2 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
PCI: 00:0f.3 links 0 child on link 0 NULL
PCI: 00:0f.3 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 10
PCI: 00:0f.4 links 0 child on link 0 NULL
PCI: 00:0f.4 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI: 00:0f.5 links 0 child on link 0 NULL
PCI: 00:0f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI: 00:0f.6 links 0 child on link 0 NULL
PCI: 00:0f.6 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 10
PCI: 00:0f.7 links 0 child on link 0 NULL
PCI: 00:0f.7 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:0e.0 10 * [0x0 - 0xff] io
PCI: 00:0f.0 14 * [0x400 - 0x4ff] io
PCI: 00:0f.0 20 * [0x800 - 0x87f] io
PCI: 00:0f.3 10 * [0x880 - 0x8ff] io
PCI: 00:0f.0 18 * [0xc00 - 0xc3f] io
PCI: 00:0f.0 24 * [0xc40 - 0xc7f] io
PCI: 00:0f.0 1c * [0xc80 - 0xc9f] io
PCI: 00:0f.2 20 * [0xca0 - 0xcaf] io
PCI: 00:0f.0 10 * [0xcb0 - 0xcb7] io
PCI: 00:01.0 10 * [0xcb8 - 0xcbb] io
PCI_DOMAIN: 0000 compute_resources_io: base: cbc size: cbc align: 8 gran: 0 limit: ffff done
PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:01.1 10 * [0x0 - 0xffffff] mem
PCI: 00:01.1 14 * [0x1000000 - 0x1003fff] mem
PCI: 00:01.1 18 * [0x1004000 - 0x1007fff] mem
PCI: 00:01.1 1c * [0x1008000 - 0x100bfff] mem
PCI: 00:0f.6 10 * [0x100c000 - 0x100dfff] mem
PCI: 00:0f.4 10 * [0x100e000 - 0x100efff] mem
PCI: 00:0f.5 10 * [0x100f000 - 0x100ffff] mem
PCI: 00:0f.7 10 * [0x1010000 - 0x1010fff] mem
PCI: 00:0e.0 14 * [0x1011000 - 0x10110ff] mem
PCI_DOMAIN: 0000 compute_resources_mem: base: 1011100 size: 1011100 align: 24 gran: 0 limit: ffffffff done
avoid_fixed_resources: PCI_DOMAIN: 0000
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: PCI_DOMAIN: 0000
constrain_resources: PCI: 00:01.0
constrain_resources: PCI: 00:01.1
constrain_resources: PCI: 00:0e.0
constrain_resources: PCI: 00:0f.0
constrain_resources: PCI: 00:0f.2
constrain_resources: PCI: 00:0f.3
constrain_resources: PCI: 00:0f.4
constrain_resources: PCI: 00:0f.5
constrain_resources: PCI: 00:0f.6
constrain_resources: PCI: 00:0f.7
avoid_fixed_resources2: PCI_DOMAIN: 0...@10000000 limit 0000ffff
lim->base 00000400 lim->limit 0000ffff
avoid_fixed_resources2: PCI_DOMAIN: 0...@10000100 limit ffffffff
lim->base 1f7e0000 lim->limit febfffff
Setting resources...
PCI_DOMAIN: 0000 allocate_resources_io: base:400 size:cbc align:8 gran:0 limit:ffff
Assigned: PCI: 00:0e.0 10 * [0x400 - 0x4ff] io
Assigned: PCI: 00:0f.0 14 * [0x800 - 0x8ff] io
Assigned: PCI: 00:0f.0 20 * [0xc00 - 0xc7f] io
Assigned: PCI: 00:0f.3 10 * [0xc80 - 0xcff] io
Assigned: PCI: 00:0f.0 18 * [0x1000 - 0x103f] io
Assigned: PCI: 00:0f.0 24 * [0x1040 - 0x107f] io
Assigned: PCI: 00:0f.0 1c * [0x1080 - 0x109f] io
Assigned: PCI: 00:0f.2 20 * [0x10a0 - 0x10af] io
Assigned: PCI: 00:0f.0 10 * [0x10b0 - 0x10b7] io
Assigned: PCI: 00:01.0 10 * [0x10b8 - 0x10bb] io
PCI_DOMAIN: 0000 allocate_resources_io: next_base: 10bc size: cbc align: 8 gran: 0 done
PCI_DOMAIN: 0000 allocate_resources_mem: base:fd000000 size:1011100 align:24 gran:0 limit:febfffff
Assigned: PCI: 00:01.1 10 * [0xfd000000 - 0xfdffffff] mem
Assigned: PCI: 00:01.1 14 * [0xfe000000 - 0xfe003fff] mem
Assigned: PCI: 00:01.1 18 * [0xfe004000 - 0xfe007fff] mem
Assigned: PCI: 00:01.1 1c * [0xfe008000 - 0xfe00bfff] mem
Assigned: PCI: 00:0f.6 10 * [0xfe00c000 - 0xfe00dfff] mem
Assigned: PCI: 00:0f.4 10 * [0xfe00e000 - 0xfe00efff] mem
Assigned: PCI: 00:0f.5 10 * [0xfe00f000 - 0xfe00ffff] mem
Assigned: PCI: 00:0f.7 10 * [0xfe010000 - 0xfe010fff] mem
Assigned: PCI: 00:0e.0 14 * [0xfe011000 - 0xfe0110ff] mem
PCI_DOMAIN: 0000 allocate_resources_mem: next_base: fe011100 size: 1011100 align: 24 gran: 0 done
Root Device assign_resources, bus 0 link: 0
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:01.1 10 <- [0x00fd000000 - 0x00fdffffff] size 0x01000000 gran 0x18 mem
PCI: 00:01.1 14 <- [0x00fe000000 - 0x00fe003fff] size 0x00004000 gran 0x0e mem
PCI: 00:01.1 18 <- [0x00fe004000 - 0x00fe007fff] size 0x00004000 gran 0x0e mem
PCI: 00:01.1 1c <- [0x00fe008000 - 0x00fe00bfff] size 0x00004000 gran 0x0e mem
PCI: 00:0e.0 10 <- [0x0000000400 - 0x00000004ff] size 0x00000100 gran 0x08 io
PCI: 00:0e.0 14 <- [0x00fe011000 - 0x00fe0110ff] size 0x00000100 gran 0x08 mem
PCI: 00:0f.0 10 <- [0x00000010b0 - 0x00000010b7] size 0x00000008 gran 0x03 io
PCI: 00:0f.0 14 <- [0x0000000800 - 0x00000008ff] size 0x00000100 gran 0x08 io
PCI: 00:0f.0 18 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
PCI: 00:0f.0 1c <- [0x0000001080 - 0x000000109f] size 0x00000020 gran 0x05 io
PCI: 00:0f.0 20 <- [0x0000000c00 - 0x0000000c7f] size 0x00000080 gran 0x07 io
PCI: 00:0f.0 24 <- [0x0000001040 - 0x000000107f] size 0x00000040 gran 0x06 io
PCI: 00:0f.2 20 <- [0x00000010a0 - 0x00000010af] size 0x00000010 gran 0x04 io
PCI: 00:0f.3 10 <- [0x0000000c80 - 0x0000000cff] size 0x00000080 gran 0x07 io
PCI: 00:0f.4 10 <- [0x00fe00e000 - 0x00fe00efff] size 0x00001000 gran 0x0c mem
PCI: 00:0f.5 10 <- [0x00fe00f000 - 0x00fe00ffff] size 0x00001000 gran 0x0c mem
PCI: 00:0f.6 10 <- [0x00fe00c000 - 0x00fe00dfff] size 0x00002000 gran 0x0d mem
PCI: 00:0f.7 10 <- [0x00fe010000 - 0x00fe010fff] size 0x00001000 gran 0x0c mem
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
Root Device links 1 child on link 0 APIC_CLUSTER: 0
APIC_CLUSTER: 0 links 1 child on link 0 APIC: 00
APIC: 00 links 0 child on link 0 NULL
PCI_DOMAIN: 0000 links 1 child on link 0 PCI: 00:01.0
PCI_DOMAIN: 0000 resource base 0 size 1f7e0000 align 0 gran 0 limit 0 flags e0004200 index 0
PCI_DOMAIN: 0000 resource base 400 size cbc align 8 gran 0 limit ffff flags 40040100 index 10000000
PCI_DOMAIN: 0000 resource base fd000000 size 1011100 align 24 gran 0 limit febfffff flags 40040200 index 10000100
PCI: 00:01.0 links 0 child on link 0 NULL
PCI: 00:01.0 resource base 10b8 size 4 align 2 gran 2 limit ffff flags 40000100 index 10
PCI: 00:01.1 links 0 child on link 0 NULL
PCI: 00:01.1 resource base fd000000 size 1000000 align 24 gran 24 limit febfffff flags 60000200 index 10
PCI: 00:01.1 resource base fe000000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 14
PCI: 00:01.1 resource base fe004000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 18
PCI: 00:01.1 resource base fe008000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 1c
PCI: 00:0e.0 links 0 child on link 0 NULL
PCI: 00:0e.0 resource base 400 size 100 align 8 gran 8 limit ffff flags 60000100 index 10
PCI: 00:0e.0 resource base fe011000 size 100 align 8 gran 8 limit febfffff flags 60000200 index 14
PCI: 00:0f.0 links 0 child on link 0 NULL
PCI: 00:0f.0 resource base 10b0 size 8 align 3 gran 3 limit ffff flags 60000100 index 10
PCI: 00:0f.0 resource base 800 size 100 align 8 gran 8 limit ffff flags 60000100 index 14
PCI: 00:0f.0 resource base 1000 size 40 align 6 gran 6 limit ffff flags 60000100 index 18
PCI: 00:0f.0 resource base 1080 size 20 align 5 gran 5 limit ffff flags 60000100 index 1c
PCI: 00:0f.0 resource base c00 size 80 align 7 gran 7 limit ffff flags 60000100 index 20
PCI: 00:0f.0 resource base 1040 size 40 align 6 gran 6 limit ffff flags 60000100 index 24
PCI: 00:0f.0 resource base 0 size 400 align 0 gran 0 limit ffff flags c0000100 index 1
PCI: 00:0f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
PCI: 00:0f.2 links 0 child on link 0 NULL
PCI: 00:0f.2 resource base 10a0 size 10 align 4 gran 4 limit ffff flags 60000100 index 20
PCI: 00:0f.3 links 0 child on link 0 NULL
PCI: 00:0f.3 resource base c80 size 80 align 7 gran 7 limit ffff flags 60000100 index 10
PCI: 00:0f.4 links 0 child on link 0 NULL
PCI: 00:0f.4 resource base fe00e000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10
PCI: 00:0f.5 links 0 child on link 0 NULL
PCI: 00:0f.5 resource base fe00f000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10
PCI: 00:0f.6 links 0 child on link 0 NULL
PCI: 00:0f.6 resource base fe00c000 size 2000 align 13 gran 13 limit febfffff flags 60000200 index 10
PCI: 00:0f.7 links 0 child on link 0 NULL
PCI: 00:0f.7 resource base fe010000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10
Done allocating resources.
POST: 0x88
Enabling resources...
PCI: 00:01.0 cmd <- 05
PCI: 00:01.1 subsystem <- 102d/00
PCI: 00:01.1 cmd <- 03
PCI: 00:0e.0 subsystem <- 102d/00
PCI: 00:0e.0 cmd <- 03
cs5536: cs5536_pci_dev_enable_resources()
PCI: 00:0f.0 cmd <- 09
PCI: 00:0f.2 cmd <- 01
PCI: 00:0f.3 subsystem <- 102d/00
PCI: 00:0f.3 cmd <- 01
PCI: 00:0f.4 subsystem <- 102d/00
PCI: 00:0f.4 cmd <- 02
PCI: 00:0f.5 subsystem <- 102d/00
PCI: 00:0f.5 cmd <- 02
PCI: 00:0f.6 cmd <- 02
PCI: 00:0f.7 cmd <- 02
done.
Initializing devices...
Root Device init
APIC_CLUSTER: 0 init
malloc Enter, size 1092, free_mem_ptr 00020888
malloc 00020888
Initializing CPU #0
CPU: vendor NSC device 552
CPU: family 05, model 05, stepping 02
model_gx2_init
POST: 0x60
Enabling cache
model_gx2_init DONE
CPU #0 initialized
PCI: 00:01.0 init
northbridge: northbridge_init()
irq_init_steering(00013eb0 [8000785C], 0000)
PCI: 00:01.1 init
PCI: 00:0e.0 init
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fff00000 + 38 + 79ee + align -> fff07a40
Check fallback/payload
CBFS: follow chain: fff07a40 + 38 + 11038 + align -> fff18ac0
Check vsa
CBFS: follow chain: fff18ac0 + 28 + e228 + align -> fff26d40
Check
CBFS: follow chain: fff26d40 + 28 + c9278 + align -> ffff0000
CBFS: Could not find file pci10ec,8139.rom
PCI: 00:0f.0 init
cs5536: southbridge_init
RTC Init
GPIO_ADDR: 00000800
uarts_init: enable COM1
uarts_init: disable COM2
cs5536: southbridge_init: enable_ide_nand_flash is 0
PCI: 00:0f.2 init
cs5536_ide: ide_init
PCI: 00:0f.3 init
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fff00000 + 38 + 79ee + align -> fff07a40
Check fallback/payload
CBFS: follow chain: fff07a40 + 38 + 11038 + align -> fff18ac0
Check vsa
CBFS: follow chain: fff18ac0 + 28 + e228 + align -> fff26d40
Check
CBFS: follow chain: fff26d40 + 28 + c9278 + align -> ffff0000
CBFS: Could not find file pci1022,2093.rom
PCI: 00:0f.4 init
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fff00000 + 38 + 79ee + align -> fff07a40
Check fallback/payload
CBFS: follow chain: fff07a40 + 38 + 11038 + align -> fff18ac0
Check vsa
CBFS: follow chain: fff18ac0 + 28 + e228 + align -> fff26d40
Check
CBFS: follow chain: fff26d40 + 28 + c9278 + align -> ffff0000
CBFS: Could not find file pci1022,2094.rom
PCI: 00:0f.5 init
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fff00000 + 38 + 79ee + align -> fff07a40
Check fallback/payload
CBFS: follow chain: fff07a40 + 38 + 11038 + align -> fff18ac0
Check vsa
CBFS: follow chain: fff18ac0 + 28 + e228 + align -> fff26d40
Check
CBFS: follow chain: fff26d40 + 28 + c9278 + align -> ffff0000
CBFS: Could not find file pci1022,2095.rom
PCI: 00:0f.6 init
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fff00000 + 38 + 79ee + align -> fff07a40
Check fallback/payload
CBFS: follow chain: fff07a40 + 38 + 11038 + align -> fff18ac0
Check vsa
CBFS: follow chain: fff18ac0 + 28 + e228 + align -> fff26d40
Check
CBFS: follow chain: fff26d40 + 28 + c9278 + align -> ffff0000
CBFS: Could not find file pci1022,2096.rom
PCI: 00:0f.7 init
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fff00000 + 38 + 79ee + align -> fff07a40
Check fallback/payload
CBFS: follow chain: fff07a40 + 38 + 11038 + align -> fff18ac0
Check vsa
CBFS: follow chain: fff18ac0 + 28 + e228 + align -> fff26d40
Check
CBFS: follow chain: fff26d40 + 28 + c9278 + align -> ffff0000
CBFS: Could not find file pci1022,2097.rom
Devices initialized
Show all devs...After init.
Root Device: enabled 1, 0 resources
APIC_CLUSTER: 0: enabled 1, 0 resources
APIC: 00: enabled 1, 0 resources
PCI_DOMAIN: 0000: enabled 1, 3 resources
PCI: 00:01.0: enabled 1, 1 resources
PCI: 00:01.1: enabled 1, 4 resources
PCI: 00:0e.0: enabled 1, 2 resources
PCI: 00:0f.0: enabled 1, 8 resources
PCI: 00:0f.2: enabled 1, 1 resources
PCI: 00:0f.3: enabled 1, 1 resources
PCI: 00:0f.4: enabled 1, 1 resources
PCI: 00:0f.5: enabled 1, 1 resources
PCI: 00:0f.6: enabled 1, 1 resources
PCI: 00:0f.7: enabled 1, 1 resources
CPU: 00: enabled 1, 0 resources
POST: 0x89
Initializing CBMEM area to 0x1f7d0000 (65536 bytes)
Adding CBMEM entry as no. 1
Moving GDT to 1f7d0200...ok
High Tables Base is 1f7d0000.
POST: 0x9a
Copying Interrupt Routing Table to 0x000f0000... done.
PIRQ Entry 0 Dev/Fn: F Slot: 5
INT: A link: 1 bitmap: 800 IRQ: 11
INT: B link: 2 bitmap: 20 IRQ: 5
INT: C link: 3 bitmap: 400 IRQ: 10
INT: D link: 4 bitmap: 400 IRQ: 10
Assigning IRQ 5 to 0:f.3
i8259_configure_irq_trigger: current interrupts are 0x0
i8259_configure_irq_trigger: try to set interrupts 0x20
Assigning IRQ 10 to 0:f.4
i8259_configure_irq_trigger: current interrupts are 0x20
i8259_configure_irq_trigger: try to set interrupts 0x420
Assigning IRQ 10 to 0:f.5
i8259_configure_irq_trigger: current interrupts are 0x420
i8259_configure_irq_trigger: try to set interrupts 0x420
PIRQ Entry 1 Dev/Fn: D Slot: 1
INT: A link: 4 bitmap: 400 IRQ: 10
INT: B link: 3 bitmap: 400 IRQ: 10
INT: C link: 2 bitmap: 20 IRQ: 5
INT: D link: 1 bitmap: 800 IRQ: 11
PIRQ Entry 2 Dev/Fn: E Slot: 2
INT: A link: 1 bitmap: 800 IRQ: 11
INT: B link: 2 bitmap: 20 IRQ: 5
INT: C link: 3 bitmap: 400 IRQ: 10
INT: D link: 4 bitmap: 400 IRQ: 10
Assigning IRQ 11 to 0:e.0
i8259_configure_irq_trigger: current interrupts are 0x420
i8259_configure_irq_trigger: try to set interrupts 0xc20
PIRQ1: 11
PIRQ2: 5
PIRQ3: 10
PIRQ4: 10
Adding CBMEM entry as no. 2
Copying Interrupt Routing Table to 0x1f7d0400... done.
PIRQ Entry 0 Dev/Fn: F Slot: 5
INT: A link: 1 bitmap: 800 IRQ: 11
INT: B link: 2 bitmap: 20 IRQ: 5
INT: C link: 3 bitmap: 400 IRQ: 10
INT: D link: 4 bitmap: 400 IRQ: 10
Assigning IRQ 5 to 0:f.3
i8259_configure_irq_trigger: current interrupts are 0xc20
i8259_configure_irq_trigger: try to set interrupts 0xc20
Assigning IRQ 10 to 0:f.4
i8259_configure_irq_trigger: current interrupts are 0xc20
i8259_configure_irq_trigger: try to set interrupts 0xc20
Assigning IRQ 10 to 0:f.5
i8259_configure_irq_trigger: current interrupts are 0xc20
i8259_configure_irq_trigger: try to set interrupts 0xc20
PIRQ Entry 1 Dev/Fn: D Slot: 1
INT: A link: 4 bitmap: 400 IRQ: 10
INT: B link: 3 bitmap: 400 IRQ: 10
INT: C link: 2 bitmap: 20 IRQ: 5
INT: D link: 1 bitmap: 800 IRQ: 11
PIRQ Entry 2 Dev/Fn: E Slot: 2
INT: A link: 1 bitmap: 800 IRQ: 11
INT: B link: 2 bitmap: 20 IRQ: 5
INT: C link: 3 bitmap: 400 IRQ: 10
INT: D link: 4 bitmap: 400 IRQ: 10
Assigning IRQ 11 to 0:e.0
i8259_configure_irq_trigger: current interrupts are 0xc20
i8259_configure_irq_trigger: try to set interrupts 0xc20
PIRQ1: 11
PIRQ2: 5
PIRQ3: 10
PIRQ4: 10
PIRQ table: 80 bytes.
POST: 0x9d
Multiboot Information structure has been written.
POST: 0x9d
Adding CBMEM entry as no. 3
Writing high table forward entry at 0x00000500
Wrote coreboot table at: 00000500 - 00000518 checksum cc61
New low_table_end: 0x00000518
Now going to write high coreboot table at 0x1f7d1400
rom_table_end = 0x1f7d1400
Adjust low_table_end from 0x00000518 to 0x00001000
Adjust rom_table_end from 0x1f7d1400 to 0x1f7e0000
Adding high table area
coreboot memory table:
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000001f7cffff: RAM
2. 000000001f7d0000-000000001f7dffff: CONFIGURATION TABLES
Wrote coreboot table at: 1f7d1400 - 1f7d159c checksum f35c
coreboot table: 412 bytes.
POST: 0x9e
0. FREE SPACE 1f7d3400 0000cc00
1. GDT 1f7d0200 00000200
2. IRQ TABLE 1f7d0400 00001000
3. COREBOOT 1f7d1400 00002000
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fff00000 + 38 + 79ee + align -> fff07a40
Check fallback/payload
Got a payload
Loading segment from rom address 0xfff07a78
data (compression=0)
malloc Enter, size 36, free_mem_ptr 00020ccc
malloc 00020ccc
New segment dstaddr 0xef000 memsize 0x11000 srcaddr 0xfff07ab0 filesize 0x11000
(cleaned up) New segment addr 0xef000 size 0x11000 offset 0xfff07ab0 filesize 0x11000
Loading segment from rom address 0xfff07a94
Entry Point 0x000fc5b8
Loading Segment: addr: 0x00000000000ef000 memsz: 0x0000000000011000 filesz: 0x0000000000011000
lb: [0x0000000000004000, 0x0000000000024000)
Post relocation: addr: 0x00000000000ef000 memsz: 0x0000000000011000 filesz: 0x0000000000011000
it's not compressed!
[ 0x00000000000ef000, 0000000000100000, 0x0000000000100000) <- 00000000fff07ab0
dest 000ef000, end 00100000, bouncebuffer 1f790000
Loaded segments
Jumping to boot code at fc5b8
POST: 0xfe
entry = 0x000fc5b8
lb_start = 0x00004000
lb_size = 0x00020000
adjust = 0x1f7ac000
buffer = 0x1f790000
elf_boot_notes = 0x00012a88
adjusted_boot_notes = 0x1f7bea88
Start bios (version 0.5.0-20091218_222750-morn.localdomain)
Found mainboard Wyse s50
Found CBFS header at 0xfffeffe0
Ram Size=0x1f7d0000
CPU Mhz=365
No apic - only the main cpu is present.
Copying PIR from 0x1f7d0400 to 0x000fdbb0
SMBIOS ptr=0x000fdb90 table=0x1f7cf800
Scan for VGA option rom
i8042 timeout on flush
Found 0 lpt ports
Found 1 serial ports
ATA controller 0 at 1f0/3f4 (irq 14 dev 7a)
ATA controller 1 at 170/374 (irq 15 dev 7a)
powerup IDE floating
powerup IDE floating
powerup IDE floating
powerup IDE floating
ata0-0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63
config_usb: 0x000fdf8c 1
ebda moved from 9f400 to 9f000
Scan for option roms
Press F12 for boot menu.
Returned 61440 bytes of ZoneHigh
e820 map has 5 items:
0: 0000000000000000 - 000000000009f000 = 1
1: 000000000009f000 - 00000000000a0000 = 2
2: 00000000000f0000 - 0000000000100000 = 2
3: 0000000000100000 - 000000001f7cf000 = 1
4: 000000001f7cf000 - 000000001f7e0000 = 2
enter handle_19:
NULL
Booting from Floppy...
Boot failed: could not read the boot disk
enter handle_18:
NULL
Booting from CD-Rom...
Boot failed: Could not read from CDROM (code 0001)
enter handle_18:
NULL
Booting from Hard Disk...
Booting from 0000:7c00
Linux version 2.6.32-4-geode (2.6.32) (r...@debian) (gcc version 4.3.2 (Debian 4.3.2-1.1) ) #1 Thu Feb 11 01:09:22 CET 2010
KERNEL supported cpus:
Intel GenuineIntel
AMD AuthenticAMD
NSC Geode by NSC
Cyrix CyrixInstead
Centaur CentaurHauls
Transmeta GenuineTMx86
Transmeta TransmetaCPU
UMC UMC UMC UMC
BIOS-provided physical RAM map:
BIOS-e820: 0000000000000000 - 000000000009f000 (usable)
BIOS-e820: 000000000009f000 - 00000000000a0000 (reserved)
BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved)
BIOS-e820: 0000000000100000 - 000000001f7cf000 (usable)
BIOS-e820: 000000001f7cf000 - 000000001f7e0000 (reserved)
DMI 2.4 present.
last_pfn = 0x1f7cf max_arch_pfn = 0x100000
init_memory_mapping: 0000000000000000-000000001f7cf000
503MB LOWMEM available.
mapped low ram: 0 - 1f7cf000
low ram: 0 - 1f7cf000
node 0 low ram: 00000000 - 1f7cf000
node 0 bootmap 00001000 - 00004efc
(6 early reservations) ==> bootmem [0000000000 - 001f7cf000]
#0 [0000000000 - 0000001000] BIOS data page ==> [0000000000 - 0000001000]
#1 [0001000000 - 00013279f4] TEXT DATA BSS ==> [0001000000 - 00013279f4]
#2 [000009f000 - 0000100000] BIOS reserved ==> [000009f000 - 0000100000]
#3 [0001328000 - 000132e049] BRK ==> [0001328000 - 000132e049]
#4 [0000007000 - 0000008000] PGTABLE ==> [0000007000 - 0000008000]
#5 [0000001000 - 0000005000] BOOTMAP ==> [0000001000 - 0000005000]
Zone PFN ranges:
DMA 0x00000000 -> 0x00001000
Normal 0x00001000 -> 0x0001f7cf
Movable zone start PFN for each node
early_node_map[2] active PFN ranges
0: 0x00000000 -> 0x0000009f
0: 0x00000100 -> 0x0001f7cf
Allocating PCI resources starting at 1f7e0000 (gap: 1f7e0000:e0820000)
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 127870
Kernel command line: root=/dev/hda2 ro console=ttyS0,115200n8 console=tty0 gxfb.mode_option=1280x1...@60. noapic nolapic acpi=off
PID hash table entries: 2048 (order: 1, 8192 bytes)
Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
Initializing CPU#0
Memory: 507620k/515900k available (1855k kernel code, 7712k reserved, 786k data, 228k init, 0k highmem)
virtual kernel memory layout:
fixmap : 0xfffe5000 - 0xfffff000 ( 104 kB)
vmalloc : 0xdffcf000 - 0xfffe3000 ( 512 MB)
lowmem : 0xc0000000 - 0xdf7cf000 ( 503 MB)
.init : 0xc1295000 - 0xc12ce000 ( 228 kB)
.data : 0xc11cfcd4 - 0xc12947e0 ( 786 kB)
.text : 0xc1000000 - 0xc11cfcd4 (1855 kB)
Checking if this processor honours the WP bit even in supervisor mode...Ok.
SLUB: Genslabs=13, HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
Hierarchical RCU implementation.
NR_IRQS:16
Console: colour dummy device 80x25
console [tty0] enabled
console [ttyS0] enabled
Fast TSC calibration using PIT
Detected 365.221 MHz processor.
Calibrating delay loop (skipped), value calculated using timer frequency.. 730.44 BogoMIPS (lpj=1460884)
Mount-cache hash table entries: 512
CPU: L1 I Cache: 16K (32 bytes/line), D cache 16K (32 bytes/line)
CPU: NSC Geode(TM) Integrated Processor by National Semi stepping 02
Checking 'hlt' instruction... OK.
NET: Registered protocol family 16
geode-mfgpt: 2 MFGPT timers available.
geode-mfgpt: Registered timer 0
mfgpt-timer: Registering MFGPT timer 0 as a clock event, using IRQ 7
PCI: Using configuration type 1 for base access
bio: create slab <bio-0> at 0
ACPI: Interpreter disabled.
vgaarb: loaded
SCSI subsystem initialized
PCI: Probing PCI hardware
pci 0000:00:0e.0: PME# supported from D1 D2 D3hot
pci 0000:00:0e.0: PME# disabled
pci 0000:00:0f.4: PME# supported from D0 D3hot D3cold
pci 0000:00:0f.4: PME# disabled
pci 0000:00:0f.5: PME# supported from D0 D3hot D3cold
pci 0000:00:0f.5: PME# disabled
vgaarb: device added: PCI:0000:00:01.1,decodes=io+mem,owns=io+mem,locks=none
pci 0000:00:0f.0: default IRQ router [1022:2090]
pci 0000:00:0f.3: BAR 0: address space collision on of device [0xc80-0xcff]
pci 0000:00:0f.3: BAR 0: can't allocate resource
Switching to clocksource tsc
pnp: PnP ACPI: disabled
NET: Registered protocol family 2
IP route cache hash table entries: 4096 (order: 2, 16384 bytes)
TCP established hash table entries: 16384 (order: 5, 131072 bytes)
TCP bind hash table entries: 16384 (order: 4, 65536 bytes)
TCP: Hash tables configured (established 16384 bind 16384)
TCP reno registered
NET: Registered protocol family 1
platform rtc_cmos: registered platform RTC device (no PNP device found)
msgmni has been set to 991
io scheduler noop registered
io scheduler anticipatory registered (default)
io scheduler deadline registered
io scheduler cfq registered
gxfb 0000:00:01.1: 8192 KiB of video memory at 0xfd000000
fbcon: Geode GX (fb0) is primary device
Console: switching to colour frame buffer device 80x30
fb0: Geode GX frame buffer device
Real Time Clock Driver v1.12b
Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a NS16550A
Uniform Multi-Platform E-IDE driver
cs5536 0000:00:0f.2: IDE controller (0x1022:0x209a rev 0x01)
cs5536 0000:00:0f.2: not 100% native mode: will probe irqs later
ide0: BM-DMA at 0x10a0-0x10a7
hda: ST9100823A, ATA DISK drive
hda: host side 80-wire cable detection failed, limiting max speed to UDMA33
hda: UDMA/33 mode selected
ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
amd74xx 0000:00:0f.2: UDMA100 controller
amd74xx 0000:00:0f.2: IDE controller (0x1022:0x209a rev 0x01)
cs5536 0000:00:0f.2: BAR 0: can't reserve I/O region [0x1f0-0x1f7]
amd74xx 0000:00:0f.2: can't reserve resources
ide_generic: please use "probe_mask=0x3f" module parameter for probing all legacy ISA IDE ports
ide-gd driver 1.18
hda: max request size: 512KiB
hda: 195371568 sectors (100030 MB) w/8192KiB Cache, CHS=16383/255/63
hda: cache flushes supported
hda: hda1 hda2 hda3 < hda5 >
8139too Fast Ethernet driver 0.9.28
8139too 0000:00:0e.0: guessed PCI INT A -> IRQ 11
eth0: RealTek RTL8139 at 0x400, 00:80:64:66:f4:1b, IRQ 11
PNP: No PS/2 controller found. Probing ports directly.
i8042.c: No controller found.
mice: PS/2 mouse device common for all mice
cpuidle: using governor ladder
cpuidle: using governor menu
Advanced Linux Sound Architecture Driver Version 1.0.21.
cs5535audio 0000:00:0f.3: guessed PCI INT B -> IRQ 5
ALSA device list:
#0: CS5535 Audio cs5535audio at 0x1400, irq 5
TCP cubic registered
NET: Registered protocol family 17
kjournald starting. Commit interval 5 seconds
EXT3-fs: mounted filesystem with writeback data mode.
VFS: Mounted root (ext3 filesystem) readonly on device 3:2.
Freeing unused kernel memory: 228k freed
udev: renamed network interface eth0 to eth1
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
ohci_hcd 0000:00:0f.4: guessed PCI INT D -> IRQ 10
ohci_hcd 0000:00:0f.4: sharing IRQ 10 with 0000:00:0f.5
ohci_hcd 0000:00:0f.4: OHCI Host Controller
ohci_hcd 0000:00:0f.4: new USB bus registered, assigned bus number 1
ohci_hcd 0000:00:0f.4: irq 10, io mem 0xfe00e000
ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
Warning! ehci_hcd should always be loaded before uhci_hcd and ohci_hcd, not after
usb usb1: New USB device found, idVendor=1d6b, idProduct=0001
usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb1: Product: OHCI Host Controller
usb usb1: Manufacturer: Linux 2.6.32-4-geode ohci_hcd
usb usb1: SerialNumber: 0000:00:0f.4
usb usb1: configuration #1 chosen from 1 choice
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 4 ports detected
ehci_hcd 0000:00:0f.5: guessed PCI INT D -> IRQ 10
ehci_hcd 0000:00:0f.5: sharing IRQ 10 with 0000:00:0f.4
ehci_hcd 0000:00:0f.5: EHCI Host Controller
ehci_hcd 0000:00:0f.5: new USB bus registered, assigned bus number 2
ehci_hcd 0000:00:0f.5: irq 10, io mem 0xfe00f000
ehci_hcd 0000:00:0f.5: USB 2.0 started, EHCI 1.00
usb usb2: New USB device found, idVendor=1d6b, idProduct=0002
usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb2: Product: EHCI Host Controller
usb usb2: Manufacturer: Linux 2.6.32-4-geode ehci_hcd
usb usb2: SerialNumber: 0000:00:0f.5
usb usb2: configuration #1 chosen from 1 choice
hub 2-0:1.0: USB hub found
hub 2-0:1.0: 4 ports detected
usb 1-2: new low speed USB device using ohci_hcd and address 2
usb 1-2: New USB device found, idVendor=046d, idProduct=c504
usb 1-2: New USB device strings: Mfr=1, Product=2, SerialNumber=0
usb 1-2: Product: USB Receiver
usb 1-2: Manufacturer: Logitech
usb 1-2: configuration #1 chosen from 1 choice
input: Logitech USB Receiver as /class/input/input0
generic-usb 0003:046D:C504.0001: input: USB HID v1.10 Keyboard [Logitech USB Receiver] on usb-0000:00:0f.4-2/input0
input: Logitech USB Receiver as /class/input/input1
generic-usb 0003:046D:C504.0002: input: USB HID v1.10 Mouse [Logitech USB Receiver] on usb-0000:00:0f.4-2/input1
usbcore: registered new interface driver usbhid
usbhid: v2.6:USB HID core driver
Adding 1951856k swap on /dev/hda5. Priority:-1 extents:1 across:1951856k
EXT3 FS on hda2, internal journal
loop: module loaded
kjournald starting. Commit interval 5 seconds
EXT3 FS on hda1, internal journal
EXT3-fs: mounted filesystem with writeback data mode.
eth1: link up, 100Mbps, full-duplex, lpa 0x41E1
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