Peter Stuge wrote: ]I have a greater problem with this; ] ]It assumes that one image will always go into one and the same size ]of flash chip.
I think I understand your concern. It is convenient to be able to use a bigger chip to test a smaller image. But limiting the decode size will only block access to the usused portion of the chip, correct? ]We can not support growing or shrinking of CBFS if we would like to, ]and hotswapping flash chips with larger size does not work. When hotswapping, shouldn't the flashing software set this register? ]I would personally prefer using the largest possible value on all ]chipsets. Despite my comments above, I agree with this. Flashing software is likely going to expand the decode to 16MB in order to run a generic chip detection algorithm, so it isn't safe to let coreboot or OS use address in that range for MMIO. As long as this area is reserved, why not just set the decode range for the whole area. Thanks, Scott ] ]//Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
