Set the ROMSIZE as 4MB. Signed-off-by: Zheng Bao <zheng....@amd.com>
Index: src/southbridge/amd/sb600/Kconfig =================================================================== --- src/southbridge/amd/sb600/Kconfig (revision 6169) +++ src/southbridge/amd/sb600/Kconfig (working copy) @@ -23,6 +23,11 @@ select HAVE_USBDEBUG select TINY_BOOTBLOCK +config BOOTBLOCK_SOUTHBRIDGE_INIT + string + default "southbridge/amd/sb600/bootblock.c" + depends on SOUTHBRIDGE_AMD_SB600 + config EHCI_BAR hex default 0xfef00000 if SOUTHBRIDGE_AMD_SB600 Index: src/southbridge/amd/sb700/Kconfig =================================================================== --- src/southbridge/amd/sb700/Kconfig (revision 6169) +++ src/southbridge/amd/sb700/Kconfig (working copy) @@ -23,6 +23,11 @@ select HAVE_USBDEBUG select TINY_BOOTBLOCK +config BOOTBLOCK_SOUTHBRIDGE_INIT + string + default "southbridge/amd/sb700/bootblock.c" + depends on SOUTHBRIDGE_AMD_SB700 + config SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT bool default n Index: src/southbridge/amd/sb700/bootblock.c =================================================================== --- src/southbridge/amd/sb700/bootblock.c (revision 6169) +++ src/southbridge/amd/sb700/bootblock.c (working copy) @@ -23,12 +23,12 @@ #include <device/pci_ids.h> /* - * Enable 1MB (LPC) ROM access at 0xFFF00000 - 0xFFFFFFFF. + * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. * * Hardware should enable LPC ROM by pin straps. This function does not * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations. * - * The SB700 power-on default is to map 256K ROM space. + * The SB700 power-on default is to map 512K ROM space. * * Details: AMD SB700/710/750 BIOS Developer's Guide (BDG), Rev. 1.00, * PN 43366_sb7xx_bdg_pub_1.00, June 2009, section 3.1, page 14. @@ -39,7 +39,7 @@ device_t dev; dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, - PCI_DEVICE_ID_ATI_SB700_LPC), 0); + PCI_DEVICE_ID_ATI_SB700_LPC), 0); /* Decode variable LPC ROM address ranges 1 and 2. */ reg8 = pci_read_config8(dev, 0x48); @@ -57,8 +57,10 @@ * Enable LPC ROM range start at: * 0xfff8(0000): 512KB * 0xfff0(0000): 1MB + * 0xffe0(0000): 2MB + * 0xffc0(0000): 4MB */ - pci_write_config16(dev, 0x6c, 0xfff0); /* 1 MB */ + pci_write_config16(dev, 0x6c, 0xffc0); /* 4 MB */ /* Enable LPC ROM range end at 0xffff(ffff). */ pci_write_config16(dev, 0x6e, 0xffff); } > -----Original Message----- > From: coreboot-boun...@coreboot.org [mailto:coreboot-boun...@coreboot.org] > On Behalf Of Stefan Reinauer > Sent: Saturday, December 11, 2010 2:48 AM > To: Scott Duplichan > Cc: 'Peter Stuge'; coreboot@coreboot.org > Subject: Re: [coreboot] [PATCH] Set the register based on the ROMSIZE > > * Scott Duplichan <sc...@notabs.org> [101210 18:13]: > > Peter Stuge wrote: > > > > ]I have a greater problem with this; > > ] > > ]It assumes that one image will always go into one and the same size > > ]of flash chip. > > > > I think I understand your concern. It is convenient to be able to > > use a bigger chip to test a smaller image. But limiting the decode > > size will only block access to the usused portion of the chip, correct? > > One of the original design ideas of CBFS (or LAR in v3) was that we can > build a single image, with, say 256KB, and resize that same image later > on in case someone wants to put in fallback/normal, a linux kernel > payload or stuff like that. > > Stefan > > -- > coreboot mailing list: coreboot@coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot
sbX00_bootblock_enable_rom.patch
Description: sbX00_bootblock_enable_rom.patch
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