Pete Batard wrote: ]... ]Right now, I am especially interested in tests being conducted on AMD ]hardware to confirm that the AMD LCP/SouthBridge init works. Again, you ]should be able to test UBRX even if your platform is not supported by ]coreboot, provided of course that you can reflash your BIOS through ]external means afterwards (SPI, parallel programmer, etc.).
Hello Pete, This is an important subject because recovery is one of the few major features of a commercial BIOS that coreboot+SeaBIOS lacks. I tried the sample on ASRock E350M1 and it did not work. One reason is needed LPC clock initialization (http://permalink.gmane.org/gmane.linux.bios/67229). Another problem is the one mentioned in the release notes about cases where the serial port pins default to gpio use and must be configured for serial port use. I believe this will be the situation with Nuvoton NCT6776F. I spent a few minutes debugging with AMD simnow but was unable to get it to work there. Maybe some additional port 80 codes that mark algorithm milestones would simplify debug. Thanks, Scott -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
