Hi Scott, On 2011.07.18 04:14, Scott Duplichan wrote:
I do not have that board setup at the moment so I cannot try it without FORCE_PANIC. It seems like a baud rate change could substitute for the LPC clock frequency programming, but so far that does not work as expected.
OK. One way I see to autodetect the 48MHz or other frequencies, while not endangering a board would be to only attempt higher frequencies if the CMOS has been reset.
If we detect successful panic entry then, we store the working SB frequency to the CMOS and use it on subsequent boots. If not, we also update the CMOS, but to indicate not to try higher frequencies any more.
So I think we should have an acceptable and safe solution for generic SB800/SB900 clock detection. And of course, we could store the last successful SIO base/type/LDN in CMOS as well to bypass autodetection.
Since we're still at the PoC stage, I'll probably stick to using build options for a while, so that people willing to test do not have to reset their CMOS content.
Of course, if we can just get UART (and SIO) communication working at the default lower frequency, and have some confidence that it should work for other SIOs, which is a big "if", that would be preferred. I can probably set UBRX to try for few extra lower clock divisors on the 16550, to compensate for the lower clock.
I have an AMD SB900 board with Nuvoton NCT6776F. To make the serial port work on this board, two pieces of non-generic code are needed. 1) SIO com1 pins default to GPIO and must switched to serial port use: // logical device 2 (UART A) defaults to base 3f8, irq 4, enabled // all that is needed for early serial is to switch some dual function // pins from gpio use (default) to serial port use. Clearing cr2a bit 7 // does this. u8 reg8; pnp_enter_ext_func_mode(dev); reg8 = pnp_read_config(dev, 0x2a); reg8&= ~(1<< 7); pnp_write_config(dev, 0x2a, reg8); pnp_exit_ext_func_mode(dev);
Thanks for the info. Obviously, any SIO that sees its UARTs disabled by default will require a special case, so we will have to figure out whether they are widespread.
As long as it is limited to specific extra PnP SIO init and there aren't too many chips, A data section using a match on the chip ID should do and should offer something that can easily be updated for other chips. That's how I'm going to implement it for the NCT6776F.
2) LPC clock frequency programming and enable:
This does not look that different from SB800, so it shouldn't be too difficult to factor in. The new register at address 28 didn't exist on the SB800. Is there a public SB900 datasheet were it is documented? So far, I haven't been able to locate one?
At any rate, many thanks for the info: this is exactly the kind of data I was looking for and it will give me more food for thought.
I'll try to update UBRX to work against your SB900/NCT6776F, if you want to test it on that platform. This may take a few days.
Regards, /Pete -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
