Paul (and/or anybody else that can test this patch on a E350M1), Commit 23023a5 correctly enabled the SB800 GPP PCIe ports but didn't distribute the PCIe lanes for the GPP_CFGMODEs other than GPP_CFGMODE_X4000.
The hardware I originally tested this on only used GPP port A, so it didn't really matter if it was x1/x2/x4. The E350M1 board is evidently using two x1 channels to two PCIe devices so it needs the lanes distributed correctly. I wanted to know if anybody could test this on a E350M1 to see if it fixes the problem. Any takers? Thanks, Dave From ee0af1d0478ddbe67562fe7e967fb419f85a3ade Mon Sep 17 00:00:00 2001 From: Dave Frodin <[email protected]> Date: Wed, 17 Apr 2013 08:51:49 -0600 Subject: [PATCH] AMD/SB800: Define the GPP PCIe lane distribution A bug was created with commit 23023a5 which correctly enabled the GPP PCIe ports, but didn't distribute the 4 PCIe lanes to those ports. Change-Id: I1dc7eaa59ad0a49be0e6e59f5ee40c4c121a5110 Signed-off-by: Dave Frodin <[email protected]> --- src/southbridge/amd/cimx/sb800/late.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index cfdf9f2..74b2d08 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -368,13 +368,13 @@ static void sb800_enable(device_t dev) /* the first sb800 device */ switch (GPP_CFGMODE) { /* config the GPP PCIe ports */ case GPP_CFGMODE_X2200: - abcfg_reg(0xc0, 0x01FF, 0x030); /* x2 Port_0, x2 Port_1 */ + abcfg_reg(0xc0, 0x01FF, 0x032); /* x2 Port_0, x2 Port_1 */ break; case GPP_CFGMODE_X2110: - abcfg_reg(0xc0, 0x01FF, 0x070); /* x2 Port_0, x1 Port_1&2 */ + abcfg_reg(0xc0, 0x01FF, 0x073); /* x2 Port_0, x1 Port_1&2 */ break; case GPP_CFGMODE_X1111: - abcfg_reg(0xc0, 0x01FF, 0x0F0); /* x1 Port_0&1&2&3 */ + abcfg_reg(0xc0, 0x01FF, 0x0F4); /* x1 Port_0&1&2&3 */ break; case GPP_CFGMODE_X4000: default: -- 1.7.9 ----- Original Message ----- > From: "Paul Menzel" <[email protected]> > To: "openvoid" <[email protected]> > Cc: [email protected] > Sent: Tuesday, April 16, 2013 9:04:22 AM > Subject: Re: [coreboot] AsRock E350M1 report: Ethernet adapter not initialized > > Dear openvoid, > > > welcome to coreboot and thank you for your report! > > > Am Sonntag, den 14.04.2013, 22:09 +0400 schrieb openvoid: > > > I get E350M1 motherboard > > In #coreboot on <irc.freenode.net> openvoid confirmed that this is the > ASRock E350M1 and not the ASRock E350M1/USB3. > > > and want to report some things i tested. > > Thanks. I assume you also opened the ticket 192 in coreboot’s Trac > instance [1]. Thanks for this, but we should try to keep discussing this > on this list (one thread for each problem) as the Trac tracker is not > used that much anymore. > > What payload do you use? > > > This can be especially interesting to Paul Menzel and some others, who > > i see adding patches related to this motherboard few last months. > > Yes, thanks a lot! > > > Most information is available on http://www.coreboot.org/ASRock_E350M1 > > so i post only difference with my experience. > > […] > > > I cannot surely say after which commit regressions occur. I was using > > gcb891de as latest > > The g at the very beginning stands for git, so here is the revision you > reference. > > $ git show cb891de > commit cb891de07ffe605897010776fc1becc9589d3648 > Author: Paul Menzel <[email protected]> > Date: Sat Apr 13 18:35:32 2013 +0200 > > cbmem: parse_cbtable: Use length modifier `ll` `u64` > argument > > Reviewed-on: http://review.coreboot.org/3084 > > > and ec6f043 as old surely working (most close to latest progressive > > changes on wiki page). > > $ git show ec6f043 > commit ec6f043c253355483bd065c39adc91bad2647ee9 > Author: Denis 'GNUtoo' Carikli <[email protected]> > Date: Thu Jun 14 14:19:09 2012 +0200 > > llshell: fix build without romcc > > Reviewed-on: http://review.coreboot.org/1101 > > I have reordered your message, so I can comment on the problems now. > > > Wiki update: > > PS/2 Keyboard - NOT working - with init_ps2_keyboard option it blinks > > during post but still not working in OS > > PS/2 Mouse - NOT working > > I have different experience. Once it did not work at all. The other time > it worked somewhat but pressing one key it appeared several times on the > screen as reported to the list [2][3]. > > > Regressions: > > Ethernet - NOT working > > Thanks for finding the responsible in [1] using bisection! > > > POST time 5-10 seconds instead of 1-3 > > Same here. Please see my message to the mailing list [4] > > > Thanks, > > Paul > > > [1] https://tracker.coreboot.org/trac/coreboot/ticket/192 > [2] http://www.coreboot.org/pipermail/coreboot/2013-March/075584.html > [3] http://www.coreboot.org/pipermail/coreboot/2013-April/075586.html > [4] http://www.coreboot.org/pipermail/coreboot/2013-April/075602.html > > -- > coreboot mailing list: [email protected] > http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
