Hi Frederico, On 26.11.2016 22:57, Federico Amedeo Izzo wrote: > On 11/23/2016 10:14 AM, Zoran Stojsavljevic wrote: >> >> Federico, I have here also suggestion for you. You should try to run >> only one DDR memory stick, and then record the memory values (since I >> see from your logs that they are identical for both memories/DDRs), >> and then to try to hard-code them for both sticks, altogether avoiding >> raminit.c setup, and see if this improves your situation?! > > Hi Zoran and others, > > I finally flashed again coreboot after trying the Lenovo BIOS. > I used the decode-dimms util to dump RAM info while on the Lenovo BIOS > with both RAM sticks, > and run the same program on the coreboot BIOS with just one stick. > > Sadly the output on coreboot is the same of the output on Lenovo BIOS so > no info gained by this.
this is pretty much expected. `decode-dimms` reads the SPD ROM on the DIMM. It's just static data about the timings that the DIMM supports. You can read the current configuration of the memory controller with `inteltool -m` (you'll find it in util/inteltool/ of the coreboot tree). Hope that helps, Nico > > I will attach the output from the Lenovo BIOS in case it turns out useful. > > The next step I will try will be to modify raminit.c of Nehalem to > accept hardcoded frequency as SandyBridge does, > hoping that this will be a temporary fix to get the two DIMMs working. > > > > -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot