* John Lewis <jle...@johnlewis.ie> [170227 10:38]: > Hi Naveed, > > It's probably the MRC cache or something like that, which IIRC you can > disable.
This is correct. Unfortunately, if you disable the MRC cache you will lose functionality like the ability to resume from S3 suspend, and your boot time will go up between 300ms and 30 some seconds, depending on the chipset you are looking at. Stefan > Whether there is also something else writing to the chip from coreboot I'm not > 100% but others will chime in on that, I'm sure. > > Kind Regards, > > John. > > > On 27/02/17 08:15, Naveed Ghori wrote: > > > Hi all, > > Does Coreboot write to the flash chip it resides on? Can this be disabled? > > Verify of the SPI bios chip fails once the unit has booted up at least > once. > > � > > Best Regards, > > Naveed > > Naveed Ghori | Lead Firmware & Driver Engineer > DTI Group Ltd | Transit Security & Surveillance > 31 Affleck Road, Perth Airport, Western Australia 6105, Australia > P +61 8 9373 2905,151 | F +61 8 9479 1190 |�naveed.gh...@dti.com.au > Visit our website��www.dti.com.au > The information contained in this email is confidential. If you receive > this email in error, please inform DTI Group Ltd via the above contact > details. If you are not the intended recipient, you may not use or > disclose > the information contained in this email or attachments. > > > > > -- > coreboot mailing list: coreboot@coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot
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