Am 22.04.19 um 11:13 schrieb Mike Banon: > For some reason the config inside your rom is trimmed and includes > just 5 lines: > > # This image was built using coreboot 4.9-1334-gdb3f0e3ebd-dirty > CONFIG_VENDOR_ASUS=y > CONFIG_BOARD_ASUS_F2A85_M=y > CONFIG_HUDSON_XHCI_FWM=y > # CONFIG_DRIVERS_INTEL_WIFI is not set > > Perhaps that's indeed the only difference from default config - but > why IOMMU wasn't working initially, then? That's still a mystery, and > I would appreciate if you could send the full .config from your > coreboot build directory to complete the investigation.
YES indeed this is the diff from the default config. .config locally also seems to works like this now > > By the way, I noticed that you have CONFIG_HUDSON_XHCI_FWM=y . > Enabling the CONFIG_HUDSON_XHCI_ENABLE / CONFIG_HUDSON_XHCI_FWM > options results in XHCI blob being added to your coreboot image - it > is hidden inside the " apu/amdfw 0x1fdc0 raw 66048 ". If you'd like > your coreboot build to get closer to libreboot, you could get rid of > XHCI blob by disabling these options. Yeah i am aware of this, but i would like to use USB3 > > Also, it seems that you either forgot to add the AtomBIOS blob for > your integrated GPU (pci1002,****.rom), or plan to use this board in a > headless mode. I'm not sure if it is possible to get the graphical > output without it... ( if I'm wrong, how are you getting it? using > that Nvidia GT210 which is running its' own blob? ) > Yeah i am using that nvidia card, as it works with nouveau with no addional blob on OS level > Best regards, > Mike Banon > > On Mon, Apr 22, 2019 at 8:42 AM Kinky Nekoboi > <kinky_neko...@nekoboi.moe> wrote: > > Here is the filelink: > > https://nekoboi.moe/nextcloud/index.php/s/DfYGsdNzHHxGKHA > > the .config file should be included in the rom. > > Am 21.04.19 um 20:13 schrieb Mike Banon: >> SMU is still inside your coreboot build, it's just hardcoded as >> an array of hex values inside the >> >> ./coreboot/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h >> file. That's why you couldn't see SMU firmware as a separate >> binary at your CBFS. Just like a microcode, which is also set up >> inside some .c/.h files. Yes, please send your working build when >> it's possible, and also your current ./coreboot/.config please - >> this is also very important. >> >> Have a nice weekends ;-) >> >> On Sun, Apr 21, 2019 at 6:36 PM Kinky Nekoboi >> <kinky_neko...@nekoboi.moe> <mailto:kinky_neko...@nekoboi.moe> wrote: >> >> Yes IOMMU works fine with 0x0600111f microcode. >> >> No i dont tried the reversed eng. SMU when it is no already >> inside coreboot. >> >> I wasnt able to send an email attached with my rom file ... i >> am not at home right now so i will provied your with a file >> link to my rom later .. proberally on Tuesday. >> >> IMC was dropped out of the standart config and also out of >> the nconfig menu as i experienced. You can see this in the >> absensce of fan control ( what is not problem if you have a >> FAN that is not extrem loud at 12V) >> >> Am 21.04.19 um 09:29 schrieb Mike Banon: >>> So IOMMU is working for you even with 0x0600111f microcode >>> installed? That's very good. I wonder what was wrong >>> initially, and hope that you could send a board status >>> report or - at least - please upload your current .config to >>> somewhere (e.g. pastebin) and post a link! >>> >>> > are there any other blobs present in my rom now besides >>> microcode ? >>> >>> The microcode blob has been present in your coreboot even >>> before my ucode.sh patch, it just was an older 0x0600110f >>> version (more vulnerable to some spectres and perhaps more >>> buggy IOMMU - e.g. at our G505S we could get IOMMU working >>> properly only with this 0x0600111f update). >>> >>> > my build rom in attachment for inspection >>> >>> I can't see it - perhaps the mailing list didn't accept this >>> big attachment. >>> >>> > AMD SMU firmware >>> >>> Have you tried running this free firmware replacement >>> (https://github.com/zamaudio/smutool/) and is it working? >>> >>> You could also check about the IMC. Read the latest messages >>> at this page: >>> >>> https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/IAFQRF7264GGQRNEWLUKGRUO4KSHTELB/ >>> They contain the instructions about how to check that your >>> IMC is inactive >>> >>> On Sat, Apr 20, 2019 at 11:11 AM Kinky Nekoboi >>> <kinky_neko...@nekoboi.moe> >>> <mailto:kinky_neko...@nekoboi.moe> wrote: >>> >>> >>> >>> >>> -------- Weitergeleitete Nachricht -------- >>> Betreff: Re: [coreboot] Re: Fwd: Re: Fwd: F2A85M IOMMU >>> still not working for RIchland CPUS >>> Datum: Thu, 18 Apr 2019 16:24:42 +0200 >>> Von: Kinky Nekoboi <kinky_neko...@nekoboi.moe> >>> <mailto:kinky_neko...@nekoboi.moe> >>> An: Mike Banon <mikeb...@gmail.com> >>> <mailto:mikeb...@gmail.com>, coreboot@coreboot.org >>> <mailto:coreboot@coreboot.org> >>> >>> >>> >>> did this. >>> >>> sudo dmesg | grep microcode >>> [ 1.177705] microcode: CPU0: patch_level=0x0600111f >>> [ 1.177708] microcode: CPU1: patch_level=0x0600111f >>> [ 1.177715] microcode: CPU2: patch_level=0x0600111f >>> [ 1.177722] microcode: CPU3: patch_level=0x0600111f >>> [ 1.177761] microcode: Microcode Update Driver: v2.2. >>> >>> works like a charm. >>> >>> please inform me if this is still the case: (from >>> libreboot side) >>> >>> are there any other blobs present in my rom now besides >>> microcode ? >>> >>> /* my build rom in attachment for inspection. (no vbios >>> included as i mentioned before radeon gpus are not >>> working, i am running an NV GT210 atm) >>> >>> */ >>> >>> >>> AMD SMU firmware >>> >>> Handles some power management for PCIe devices (without >>> this, your laptop will not work properly) and several >>> other power management related features. >>> >>> The firmware is signed, although on older AMD hardware >>> it is a symmetric key, which means that with access to >>> the key (if leaked) you could sign your own modified >>> version and run it. Rudolf Marek (coreboot hacker) found >>> out how to extract this key in this video demonstration >>> >>> <https://media.ccc.de/v/31c3_-_6103_-_en_-_saal_2_-_201412272145_-_amd_x86_smu_firmware_analysis_-_rudolf_marek>, >>> and based on this work, Damien Zammit (another coreboot >>> hacker) partially replaced it >>> <https://github.com/zamaudio/smutool/> with free >>> firmware, but on the relevant system (ASUS F2A85-M) >>> there were still other blobs present (Video BIOS, and >>> others) preventing the hardware from being supported in >>> libreboot. >>> >>> Am 18.04.19 um 15:08 schrieb Mike Banon: >>>> Thank you, Nekoboi. If I understand it correctly: you >>>> haven't changed anything at coreboot or its' >>>> configuration, but your IOMMU suddenly started to work? >>>> ;-) (unknown what got it working?) Also, please could >>>> you make almost the same coreboot build, with the only >>>> difference is these microcodes installed by the >>>> unofficial patch: >>>> >>>> http://dangerousprototypes.com/docs/Lenovo_G505S_hacking#AMD_microcode_updates >>>> , and then try it again with the same Linux to see if >>>> it's still working. With this patch applied, the >>>> microcode level should be 0x0600111f (...1f instead of >>>> ...0f) to confirm the successful installation. >>>> >>>> On Thu, Apr 18, 2019 at 1:35 PM Kinky Nekoboi >>>> <kinky_neko...@nekoboi.moe> >>>> <mailto:kinky_neko...@nekoboi.moe> wrote: >>>> >>>> IOMMU and system still booting without linux kernel >>>> level microcode >>>> >>>> Am 18.04.19 um 11:38 schrieb Kinky Nekoboi: >>>>> >>>>> >>>>> >>>>> >>>>> -------- Weitergeleitete Nachricht -------- >>>>> Betreff: Re: [coreboot] Re: Fwd: F2A85M IOMMU >>>>> still not working for RIchland CPUS >>>>> Datum: Thu, 18 Apr 2019 11:38:16 +0200 >>>>> Von: Kinky Nekoboi <kinky_neko...@nekoboi.moe> >>>>> <mailto:kinky_neko...@nekoboi.moe> >>>>> An: Mike Banon <mikeb...@gmail.com> >>>>> <mailto:mikeb...@gmail.com> >>>>> >>>>> >>>>> >>>>> CPU : A8-6600K >>>>> >>>>> [ 1.271514] microcode: CPU0: patch_level=0x0600110f >>>>> [ 1.271521] microcode: CPU1: patch_level=0x0600110f >>>>> [ 1.271532] microcode: CPU2: patch_level=0x0600110f >>>>> [ 1.271538] microcode: CPU3: patch_level=0x0600110f >>>>> [ 1.271583] microcode: Microcode Update Driver: >>>>> v2.2. >>>>> i compiled from the master tree, build on 16. >>>>> April 2019 >>>>> >>>>> no microcode was included in that build. >>>>> >>>>> next step i will try if, the problems occur again >>>>> if i remove microcode >>>>> updates via llinux kernel. >>>>> >>>>> here is cbmem output as attachment >>>>> >>>>> Am 18.04.19 um 06:08 schrieb Mike Banon: >>>>>>> also it seems that IOMMU is working now... >>>>>> Congratulations with these amazing news! Please tell, >>>>>> what version of >>>>>> coreboot you've currently installed? Also, have you used >>>>>> this >>>>>> microcode updating patch from DangerousPrototypes page >>>>>> before building >>>>>> your current coreboot build? >>>>>> >>>>>>> maybe cause i have microcode updates in the kernel >>>>>>> included this time ? >>>>>> By the way, the microcode updates provided by Linux are >>>>>> _older_ than >>>>>> what this "microcode updating patch" is providing : >>>>>> simply because AMD >>>>>> has shared their latest update with some proprietary >>>>>> UEFI makers but >>>>>> didn't share them with the opensource world (and so we >>>>>> had to get them >>>>>> by manually extracting). But if the kernel sees that a >>>>>> newer microcode >>>>>> version is loaded, it doesn't replace it. Please, could >>>>>> you check and >>>>>> tell, what microcode version do you see as installed? >>>>> >>>>> >>>>> _______________________________________________ >>>>> coreboot mailing list -- coreboot@coreboot.org >>>>> <mailto:coreboot@coreboot.org> >>>>> To unsubscribe send an email to >>>>> coreboot-le...@coreboot.org <mailto:coreboot-le...@coreboot.org> >>>> _______________________________________________ >>>> coreboot mailing list -- coreboot@coreboot.org >>>> <mailto:coreboot@coreboot.org> >>>> To unsubscribe send an email to >>>> coreboot-le...@coreboot.org >>>> <mailto:coreboot-le...@coreboot.org> >>>> >>>> >>>> _______________________________________________ >>>> coreboot mailing list -- coreboot@coreboot.org >>>> <mailto:coreboot@coreboot.org> >>>> To unsubscribe send an email to coreboot-le...@coreboot.org >>>> <mailto:coreboot-le...@coreboot.org> >>> _______________________________________________ >>> coreboot mailing list -- coreboot@coreboot.org >>> <mailto:coreboot@coreboot.org> >>> To unsubscribe send an email to >>> coreboot-le...@coreboot.org >>> <mailto:coreboot-le...@coreboot.org> >>> >>> >>> _______________________________________________ >>> coreboot mailing list -- coreboot@coreboot.org >>> <mailto:coreboot@coreboot.org> >>> To unsubscribe send an email to coreboot-le...@coreboot.org >>> <mailto:coreboot-le...@coreboot.org> >> >> >> _______________________________________________ >> coreboot mailing list -- coreboot@coreboot.org >> <mailto:coreboot@coreboot.org> >> To unsubscribe send an email to coreboot-le...@coreboot.org >> <mailto:coreboot-le...@coreboot.org> >
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