Hello Shreesh, 03.05.19 11:35, Shreesh Chhabbi wrote: > MRC inside FSP is designed this way for reason that Soldered Memory > will not be replaced on a particular design,
I have little experience with memory-down configurations. But still, all the boards I know from the coreboot tree, they have options for memory chips from different vendors. > hence developer could hardcode parameters for that > memory device. However for SODIMM, we could use DIMM from any > vendor/configuration. Hence it needs to be dynamically determined. Either interface can be fed with dynamic data. My interpretation was always that it is simply uncommon to solder an SPD EEPROM to a main- board, because you can integrate the data into the firmware. But that doesn't mean, you can't switch chips. Nico _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
