On Wed, May 22, 2019 at 6:14 PM Дмитрий Понаморев <dponamo...@gmail.com> wrote: > > The controversial decision but the console output is not connected directly > to the processor but to the superio Nuvoton. > I did not find any settings to enable LPC (LPC_EN) for the Atom C2000 to. > In atom-c2000-microserver-datasheet-334978.pdf I found register LPCC (LPC > control register). > This register includes LPC_CLKOUT1. As far as I understood, the nuvoton uses > this signal. >
Okay then. The paragraphs of datasheet you should be interested are: 24.2.4 about the LPC routing rules. It says anything not positively decoded by SOC integrated peripherals will be routed to LPC. 20.2 and 20.3 to disable the SoC's integrated UART devices. When enabled, they would positively decode 0x3f8 and 0x2f8 (bases) and prevent those from being routed to LPC controller. If you previously did not have LPC_CLK running for the Nuvoton part in your coreboot build, it explains why util/superiotool did not detect Nuvoton. If you did not do so already, run that tool again. Hopefully you see something on 0x4e now. SuperIOs typically have another clock input pin (either 24 MHz or 48 MHz) for the baud generator of the UARTs. If you get that Nuvoton detected, and disable SoC UARTs, and still have no serial output, I would trace the source for that clock next. Regards, Kyösti _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
