Thank for help! The LPC_CLKOUT1 clock signal appeared but there is no nuvoton chip detected in linux.
I could not turn off the SOC UART yet. With my changes, the system does not start well (stops at post code 0x46, 0x47). /*Disabled SOC UART1 & UART2*/ u32 reg32; reg32 = pci_read_config32(SOC_LPC_DEV /*(0,1f,0)*/, UART_CONT /*0x80*/); reg32 = reg32 & (~0x3); pci_write_config32(SOC_LPC_DEV, UART_CONT, reg32); And the most important thing is that the Nuvoton System Clock (48 MHz for the baud generator of the UARTs) is missing. IDT clock synthesizer (9VRS4420DKLFT) is responsible for the formation of this clock. This clock synthesizer provides reference clocks for I/O interfaces, SATA, USB, Gbe and PCI Express. At the initial moment of time, the clock synthesizer is initialized via the SMB bus (I can see it with an oscilloscope). But no 48 MHz clock for Nuvoton. Nuvoton System Clock, use the USB_48M_2X contact of 9VRS4420DKLFT, which is normally not used. How can I change the IDT clock synthesizer (9VRS4420DKLFT) settings in coreboot? Rather, where can I make changes in coreboot to properly configure IDT clock synthesizer (9VRS4420DKLFT)? Best Regards, Dmitry Ponamorev ср, 22 мая 2019 г. в 21:46, Kyösti Mälkki <kyosti.mal...@gmail.com>: > On Wed, May 22, 2019 at 6:14 PM Дмитрий Понаморев <dponamo...@gmail.com> > wrote: > > > > The controversial decision but the console output is not connected > directly to the processor but to the superio Nuvoton. > > I did not find any settings to enable LPC (LPC_EN) for the Atom C2000 to. > > In atom-c2000-microserver-datasheet-334978.pdf I found register LPCC > (LPC control register). > > This register includes LPC_CLKOUT1. As far as I understood, the nuvoton > uses this signal. > > > > Okay then. The paragraphs of datasheet you should be interested are: > > 24.2.4 about the LPC routing rules. It says anything not positively > decoded by SOC integrated peripherals will be routed to LPC. > > 20.2 and 20.3 to disable the SoC's integrated UART devices. When > enabled, they would positively decode 0x3f8 and 0x2f8 (bases) and > prevent those from being routed to LPC controller. > > If you previously did not have LPC_CLK running for the Nuvoton part in > your coreboot build, it explains why util/superiotool did not detect > Nuvoton. If you did not do so already, run that tool again. Hopefully > you see something on 0x4e now. > > SuperIOs typically have another clock input pin (either 24 MHz or 48 > MHz) for the baud generator of the UARTs. If you get that Nuvoton > detected, and disable SoC UARTs, and still have no serial output, I > would trace the source for that clock next. > > Regards, > Kyösti >
_______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
