Hi Matt!
The native RAM initialization for SNB/IVB currently lacks ECC support;
there are two patches in Gerrit (22214 & 22215) that add part of the ECC
support, but IIRC they still lack support for clearing the RAM after a
cold boot. If you don't clear the ECC RAM there, you'll probably get a
whole lot of ECC errors, since the RAM contents are random-ish before
that and so at least for some words the error correction bits will be
wrong before that.
As far as I've seen the board doesn't contain a BMC, so you don't have
to poke some undocumented registers in it to have the SPD EEPROMS on the
DIMMs connected to the PCH's SMBus. That was an issue when lynxis and I
started porting the HP gen 8 microserver; someone else figured that out
in the meantime, but I think that's not published yet.
The SNB/IVB CPUs with 2 memory channels (laptop, desktop and small
server; basically everything except the E5/E7 Xeons from that series)
and the corresponding PCHs should be more or less supported by the
native code; some PCI-IDs or CPUIDs might be missing there, but that's
easily fixable. Ok, and some bits relating to PCIe 3 and USB3 also still
have room for improvement, but the PCH on your board doesn't have USB3
support anyway. Splitting the PEG PCIe port is also untested; I got a
board that supports that configuration, but didn't have the time to port
that one yet.
No idea how well that platform is supported by FSP/MRC; only used the
native RAM init on SNB/IVB.
C206 should be the same silicon die as the 6 series PCHs (H61, H67, ...)
with the only difference being the fuse settings.
Regards
Felix
--
Felix Held
c/o cyberkombinat23
Steinstraße 23
76133 Karlsruhe
Germany
m...@felixheld.de
Ust-ID: DE301814366
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