Dear coreboot community, I have a Tiger Lake UP3 RVP and I try to build a working coreboot on it, however facing an early stuck during CAR setup. Tried different approaches:
- native coreboot's CAR setup - the last seen post code is 0x26 - FSP-T CAR setup - the last seen post code is 0x7F (which is TempRamInit Exit event according to FSP integration guide), FSP from public repo, Client variant Used microcode from original RVP firmware. Are there any patches that I have to apply to make it working? Best regards, -- Michał Żygowski Firmware Engineer https://3mdeb.com | @3mdeb_com _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
