Hi Furquan, Tim, On 20.01.2021 10:38, Michał Żygowski wrote: > Hi Furquan, >> Do you know the microcode version that you are using? There was an >> issue with the older versions that caused a hang during NEM setup. As >> per the commit message in >> https://review.coreboot.org/c/coreboot/+/45094, it looks like you need >> 0x56 or newer microcode for enhanced NEM to work. >> >> A quick way to verify if it is the microcode version issue: Select >> INTEL_CAR_NEM instead of INTEL_CAR_NEM_ENHANCED for your board and see >> if it gets any further in the boot. >> > I have tried a few microcodes: > - the one shipped originally with RVP platform is CpuSignature: > 000806C0h, Revision: 00000064h, Date: 02.03.2020 so the revision is > newer that 0x56. > - also tried from TGL_BIOS_ww51_2020 BIOS images which has 4 blobs: > CpuSignature: 000806D1h, Revision: 00000008h, Date: 30.11.2020 > CpuSignature: 000806D0h, Revision: 0000004Eh, Date: 01.12.2020 > CpuSignature: 000806C1h, Revision: 00000072h, Date: 20.11.2020 > CpuSignature: 000806C2h, Revision: 00000002h, Date: 04.12.2020 > > It seems it have different steppings, so don't know if it really works. > > I will try to select INTEL_CAR_NEM with any of these. Thank you for the > insights. > > Best regards, Selecting INTEL_CAR_NEM did the trick. However, I am facing an issue with FSP memory training now. TGL UP3 RVP has 2 DIMMs, but the memory FSP params are set for LPDDR4. Is it intentional?
Best regards, -- Michał Żygowski Firmware Engineer https://3mdeb.com | @3mdeb_com _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
