Am Wed, Sep 08, 2021 at 06:37:17PM -0400 schrieb Benjamin Doron: > > It seems the Acer board is indeed following the Intel reference > > implementation very closely. I wrote a small table of possible values, > > the ones you extracted and some others I found be hexdumping the PE file, > > and iterated over them in a bootloop, but always got the same DEVICE_ERROR. > > > > Only after applying the Dq(s)Mapping (DqByteMapChX, DqsMapCpu2DramChX) from > > the Intel reference KabyLake board the result was FSP_SUCCESS! > > > > What do you mean that you iterated over the table of possible sets of > values? I guess it's possible that you tracked the boot number... > Additionally, I find it interesting that the Dq/Dqs settings were required. > Someday, I'd like to get to the bottom of that, but perhaps someone has, > and that's why some boards now accept the defaults in the FSP binary.
Yes, I enabled bootnum counter and flash log, and encoded a variety of possible combinations of those values in a table, and then patched drivers/intel/fsp2.0/memory_init.c to iterate over bootcounter MOD num_configs. If I got anything other than FSP_SUCCESS, full_reset() That way I could try several different configurations without reflashing between each try. By the way, during this process a thought occured to me: this process of manually poking different configurations, basically trial and error, does not scale very well. IF we have a vendor bios that does all the magic sauce, and even know something about the structure of that vendor bios, and usually have enough space in the flash to fit both coreboot and vendor bios into the same chip, why not develop a sort of debugging hypervisor that documents all the mm/io registers modified, exacting timestamps and code flow ? Such a detailed boot log of all settings could be compared between different implementations of the same platform and a new port would be much easier. // topic change Thanks again for the detailed comments on further development. The status right now is missing I2C bus, missing a few PCI devices, some stability issues with the Wifi card which I was able to activate behind a PCIe root hub, and in general higher power consumption. S3 sleep is working though! So a few things to work through, but I have to also give attention to other things outside computers. I will get back to this once time permits. By the way, the vendor bios is extremely basic. There is litterally no single setting beside the glaring necessary. It is maybe 20 settings over 5 pages, that's it. This laptop is supposed to target the computer illerates I guess. regards, Andreas _______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected]
