Hi,
On 09.09.21 00:37, Benjamin Doron wrote:
> On Wed, Sep 8, 2021 at 8:13 AM Andreas Bauer <[email protected]>
> wrote:
>
>> Am Tue, Sep 07, 2021 at 03:29:55PM -0400 schrieb Benjamin Doron:
>>> The relevant modules for setting FSP-M configuration are
>>> BoardConfigInitPreMem and possibly PlatformInitPreMem. Since the RCOMP
>> [...]
>>
>> It seems the Acer board is indeed following the Intel reference
>> implementation very closely. I wrote a small table of possible values,
>> the ones you extracted and some others I found be hexdumping the PE file,
>> and iterated over them in a bootloop, but always got the same DEVICE_ERROR.
>>
>> Only after applying the Dq(s)Mapping (DqByteMapChX, DqsMapCpu2DramChX) from
>> the Intel reference KabyLake board the result was FSP_SUCCESS!
>>
>
> What do you mean that you iterated over the table of possible sets of
> values? I guess it's possible that you tracked the boot number...
> Additionally, I find it interesting that the Dq/Dqs settings were required.
> Someday, I'd like to get to the bottom of that, but perhaps someone has,
> and that's why some boards now accept the defaults in the FSP binary.
these settings are about soldered-down memory chips and how things
are routed on the mainboard. I'm not sure if there are reasonable
FSP defaults.
AFAIK, boards with DIMM slots don't need these settings. However, due
to extensive copy-pasting such settings in the past, coreboot code made
it look like all boards would require them.
I'm very curious now how your overall settings look now. It seems
possible that FSP is using these values while it shouldn't.
On 07.09.21 21:29, Benjamin Doron wrote:
> - RCOMP targets: { 100, 40, 40, 23, 40 }, or { 100, 40, 20, 20, 26 }.
> Apparently, there is also { 60, 26, 20, 20, 26 }, but this looks different
> to what I've seen.
> - RCOMP resistors: { 200, 81, 162 }, or { 121, 75, 100 }, or { 121, 81, 100
> }
Intel provides these numbers (and what resistors are supposed to be
soldered on the board) per platform and memory combination (e.g.
1 DIMM per channel, 2, or various soldered-down configurations).
For KBL-U and SODIMMs it's 121, 81, 100; 100, 40, 20, 20, 26.
Actually, with the table at hand one can derive these numbers from other
settings and runtime detection easily. Why Intel makes FSP configuration
so complicated is a mystery. They have them in an NDA spreadsheet. They
could either put that data into coreboot or FSP but instead they prefer
to make things a PITA. Probably to keep the lie up that everything is so
complicated.
Nico
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