And your ECAM base address for PCIE is at 0xC0000000 ? From: Rao G <[email protected]> Sent: Friday, January 28, 2022 11:21 AM To: Jeff Daly <[email protected]>; coreboot <[email protected]> Subject: Re: [coreboot] SPIBAR + 0x10 offset with MMIOREAD32 causing exception
Caution: This is an external email. Please take care when clicking links or opening attachments. Yes 0xC00FD000 (Bus 0 Dev 1F Func 5) not Func 0 Thanks Rao On Fri, Jan 28, 2022 at 3:40 PM Jeff Daly <[email protected]<mailto:[email protected]>> wrote: 0xFD000 is bdf 0/1f/5, not 0/1f/0 Is your SPI controller at function 5? That’s where it usually is for Intel SoCs. From: Rao G <[email protected]<mailto:[email protected]>> Sent: Friday, January 28, 2022 8:31 AM To: coreboot <[email protected]<mailto:[email protected]>> Subject: [coreboot] SPIBAR + 0x10 offset with MMIOREAD32 causing exception Caution: This is an external email. Please take care when clicking links or opening attachments. Hi All, Trying to access SPI Flash from EFI payload 1) SpiInstance->PchSpiBase = MmPciBase ( DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SPI, PCI_FUNCTION_NUMBER_PCH_SPI ); DEBUG ((DEBUG_INFO, "PchSpiBase at 0x%x\n", SpiInstance->PchSpiBase)); >> returns PchSpiBase as 0xC00FD000 (Bus 0 Dev 1F Func 0) 2) ScSpiBar0 = MmioRead32 (SpiInstance->PchSpiBase + PCI_BASE_ADDRESSREG_OFFSET) & 0xFFFFF000; Expectation: this should return value at 0xC00FD010 Result The above code is throwing processor exception PchSpiBase at 0xC00FD000 !!!! X64 Exception Type - 0E(#PF - Page-Fault) CPU Apic ID - 00000000 !!!! ExceptionData - 0000000000000000 I:0 R:0 U:0 W:0 P:0 PK:0 SS:0 SGX:0 RIP - 00000000771903D0, CS - 0000000000000038, RFLAGS - 0000000000010046 Any clues whether SPI flash needs to be enabled in descriptor or any straps by using FIT tool? Thanks Rao
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