I'm in the process of building a new computer based on the P8ZZ7-V board with a i7-3770 CPU. I am running into a odd behavior the CPU_LED is blinking when using more than 2 8GB RAM modules. This occurs with both the vendor BIOS and the Coreboot build. A friend has the same configuration (mainboard, cpu, 4x8GB memory) which is working just fine. Which make me wonder why my setup is failing. We have gathered serial output (below) to diagnose the issue.
Most notable is that for the failing memory configurations the '[DEBUG] Stored timings CRC16 mismatch.' message is returned, after which `[DEBUG] SPD probe channel0, slot1` is triggered, which seems to fail: `ERROR: SPD CRC failed!!!` The resulting looping sequence in the logs: <start of loop> [NOTE ] coreboot-4.17 Fri Jun 3 03:10:05 UTC 2022 bootblock starting (log level: 7)... [DEBUG] FMAP: Found "FLASH" version 1.1 at 0x710000. [DEBUG] FMAP: base = 0xff800000 size = 0x800000 #areas = 4 [DEBUG] FMAP: area COREBOOT found @ 710200 (982528 bytes) [INFO ] CBFS: mcache @0xfeff0e00 built for 13 files, used 0x2dc of 0x4000 bytes [INFO ] CBFS: Found 'fallback/romstage' @0x80 size 0x14c38 in mcache @0xfeff0e2c [DEBUG] BS: bootblock times (exec / console): total (unknown) / 43 ms [NOTE ] coreboot-4.17 Fri Jun 3 03:10:05 UTC 2022 romstage starting (log level: 7)... [DEBUG] SMBus controller enabled [DEBUG] Setting up static northbridge registers... done [DEBUG] Initializing Graphics... [DEBUG] Back from systemagent_early_init() [INFO ] Intel ME early init [INFO ] Intel ME firmware is ready [DEBUG] ME: Requested 0MB UMA [DEBUG] Starting native Platform init [DEBUG] DMI: Running at X4 @ 5000MT/s [DEBUG] FMAP: area RW_MRC_CACHE found @ 700000 (65536 bytes) [DEBUG] Stored timings CRC16 mismatch. [DEBUG] ECC supported: no ECC forced: no [INFO ] ECC RAM unsupported. [DEBUG] SPD probe channel0, slot0 [DEBUG] Revision : 11 [DEBUG] Type : b [DEBUG] Key : 2 [DEBUG] Banks : 8 [DEBUG] Capacity : 4 Gb [DEBUG] Supported voltages : 1.5V [DEBUG] SDRAM width : 8 [DEBUG] Bus extension : 0 bits [DEBUG] Bus width : 64 [DEBUG] FTB timings : yes [DEBUG] Optional features : DLL-Off_mode RZQ/7 RZQ/6 [DEBUG] Thermal features : PASR ext_temp_range [DEBUG] Thermal sensor : no [DEBUG] Standard SDRAM : yes [DEBUG] Rank1 Address bits : mirrored [DEBUG] DIMM Reference card: B [DEBUG] Manufacturer ID : 9e02 [DEBUG] Part number : CML16GX3M2A1600C [DEBUG] XMP Profile : 1 [DEBUG] Max DIMMs/channel : 1 [DEBUG] XMP Revision : 1.3 [DEBUG] Requested voltage : 1500 mV [DEBUG] XMP profile supports 1 DIMMs, but 2 DIMMs are installed. [WARN ] XMP maximum DIMMs will be ignored. [INFO ] Row addr bits : 16 [INFO ] Column addr bits : 10 [INFO ] Number of ranks : 2 [INFO ] DIMM Capacity : 8192 MB [INFO ] CAS latencies : 6 9 [INFO ] tCKmin : 1.250 ns [INFO ] tAAmin : 11.250 ns [INFO ] tWRmin : 15.000 ns [INFO ] tRCDmin : 11.250 ns [INFO ] tRRDmin : 7.500 ns [INFO ] tRPmin : 11.250 ns [INFO ] tRASmin : 30.000 ns [INFO ] tRCmin : 50.625 ns [INFO ] tRFCmin : 260.000 ns [INFO ] tWTRmin : 7.500 ns [INFO ] tRTPmin : 7.500 ns [INFO ] tFAWmin : 37.500 ns [INFO ] tCWLmin : 10.000 ns [INFO ] tCMDmin : 2 [DEBUG] channel[0] rankmap = 0x3 [DEBUG] SPD probe channel0, slot1 [DEBUG] ERROR: SPD CRC failed!!! [DEBUG] Revision : 11 [DEBUG] Type : b [DEBUG] Key : 2 [DEBUG] Banks : 8 [DEBUG] Capacity : 4 Gb [DEBUG] Supported voltages : 1.5V [DEBUG] SDRAM width : 8 [DEBUG] Bus extension : 0 bits [DEBUG] Bus width : 64 <end of loop, restarting Coreboot> Mainboard: ASUS P8ZZ7-V CPU: i7-3770 RAM 4x8GB DDR3 Corsair CML16GX3M2A1600C9 Does anybody have advise what could be causing the `SPD CRC failed!!!` error? The next idea is to replace the CPU as the memory seems fine to swap around in most configurations. Other ideas are the motherboard, or something interfering with the readout. Is there an easy way to perhaps hardcode my way out of it for now, knowing the RAM will remain there once configured so I could even doe a custom Coreboot build? Best, Nico _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
