Hello, On 3.03.2023 22:33, baptx wrote: > Hello, what is the code we should change to disable E and P cores? > Should I report an issue on > https://ticket.coreboot.org/projects/coreboot/issues > <https://ticket.coreboot.org/projects/coreboot/issues> or it is already > tracked > somewhere else? Having an issue open could be useful to give more visibility > for > people who want to contribute.
Please keep replying to the list if you want people to contribute, otherwise the answers will not reach whole community. Everything is controlled by FSP UPD all you have to do is to simply disable the cores from the board code you want to build, e.g.: https://github.com/intel/FSP/blob/master/AlderLakeFspBinPkg/Client/AlderLakeS/Include/FspmUpd.h#L1509 for P cores and https://github.com/intel/FSP/blob/master/AlderLakeFspBinPkg/Client/AlderLakeS/Include/FspmUpd.h#L1706 for E cores in the FSP params functions Simple as that. Best regards, -- Michał Żygowski Firmware Engineer GPG: 6B5BA214D21FCEB2 https://3mdeb.com | @3mdeb_com
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