Hello! > IBECC (in-band ECC*) is a touted feature for the Lattepanda Mu (see > https://www.lattepanda.com/lattepanda-mu and scroll all the way down to the > bottom to the "NAS Carrier" section or > https://www.lattepanda.com/blog-323164.html). > > Does coreboot enable this feature? Is it possible to enable this feature by > modifying the FSP params set up in src/mainboard/lattepanda/mu/memory.c > or src/mainboard/lattepanda/mu/romstage_fsp_params.c? > > *where a memory controller emulates ECC by interleaving extra bits with > normal memory in ram, sacrificing some capacity for error correcting > functionality.
It doesn't look like coreboot enables that feature for the LattePanda Mu, though there is code to enable it relatively easily for Alderlake. One way is to configure it through devicetree.cb; refer to src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb [0] for an example. It can also be defined through C code such as romstage_fsp_params.c; see src/mainboard/prodrive/atlas/romstage_fsp_params.c [1] for an example. That code ties it to the option API, though you could also just hard code it. [0]: https://elixir.bootlin.com/coreboot/25.12/source/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb#L20 [1]: https://elixir.bootlin.com/coreboot/25.12/source/src/mainboard/prodrive/atlas/romstage_fsp_params.c#L56 Cheers, Nicholas _______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected]
