Hello Keshavamurthy,
> My understanding is that Raptor Lake support in Coreboot is based on the > Alder Lake platform architecture and Intel FSP integration 12, 13 and 14Gen (desktop) platforms are essentially the same. Intel supports it with singular RPL FSP as well so no matter whether you install Core i3-12100 or i9-14900 it will simply work. >I am particularly looking for guidance on the following topics: > Intel FSP requirements and integration for Raptor Lake-S Any specifics? I don't think much to say other than FSP integration guide provided by Intel and FSP headers in the tree... > DDR5 memory initialization and training Likewise. This is handled by FSP-M, so you just pass correct SMBus addresses for DIMMs in romstage. > H610 chipset configuration and board enablement > PCIe, SATA, USB, and onboard peripheral initialization src/soc/intel/alderlake/chipset_pch_s.cb > Intel ME firmware requirements This part is explained in Intel's documentation, assuming you have appropriate NDAs in place. > Boot Guard considerations during development None. Just don't do EOM or skip BootGuard provisioning altogether until you have final product that you're ready to ship. > Early boot debugging methods (UART, POST codes, external SPI flashing, etc.). Well, it's going to be a desktop board, isn't it? Just use 0x3f8 RS232 provided by SuperIO and configure it accordingly in bootblock. Recommended development workflow for a new custom mainboard port 1. Invest in EM100 (flash emulator), it will save you so much time it will essentially pay for itself. 2. Connect it to an SBC, along with RS232 to USB adapter (+null-modem terminator). 3. Add GPIO-controlled AC plug to power the system on, throw in an octocoupler for good measure to control front-panel remotely As usual, my shameless self-plug is a good "getting started" guide: https://media.ccc.de/v/38c3-corebooting-intel-based-systems I'm currently working on RaptorLake-S board since my previous workstation (src/mainboard/erying/tgl) exploded. It uses DDR4, but it doesn't matter (change memory type to DDR5 and MRC will be happy with it). Code is simple and should be indigestible even by a beginner, feel free to take a look and copy my "homework" :) (WIP, needs fixes to GPIO and some remaining misc stuff, although it's fully working aside from suspend/resume at this point): https://review.coreboot.org/c/coreboot/+/93127 On 15/06/2026 12:51, Keshavamurthy K [Firmware-NTL] via coreboot wrote: > Dear Coreboot Community, > I am currently developing a custom motherboard based on Intel Raptor Lake-S > processors and the Intel chipset with DDR5 memory support. I would like to > port Coreboot to this platform and am seeking guidance from the community > regarding board bring-up and firmware development. > My understanding is that Raptor Lake support in Coreboot is based on the > Alder Lake platform architecture and Intel FSP integration. I would > appreciate any recommendations on the best existing mainboards or reference > implementations that can be used as a starting point for a custom Raptor > Lake-S + DDR5 design. > I am particularly looking for guidance on the following topics: > > * Intel FSP requirements and integration for Raptor Lake-S. > * DDR5 memory initialization and training. > * H610 chipset configuration and board enablement. > * GPIO and pad configuration setup. > * Intel ME firmware requirements. > * Boot Guard considerations during development. > * PCIe, SATA, USB, and onboard peripheral initialization. > * Early boot debugging methods (UART, POST codes, external SPI flashing, > etc.). > * Recommended development workflow for a new custom mainboard port. > > Our goal is to bring up Coreboot on a custom Raptor Lake-S + DDR5 motherboard > intended for a custom computing platform. We are currently setting up the > build environment and reviewing existing Alder Lake and Raptor Lake > implementations within the Coreboot source tree. > Thank you for your time and support. Any documentation, examples, or > recommendations would be extremely helpful. > > Thanks & Regards, > > Keshavamurthy K > > > Note : " We Never inform change of Bank details by email. If you receive any > such emails from our domain/users. Please don’t respond, and contact us > separately " > > _______________________________________________ > coreboot mailing list -- [email protected] > To unsubscribe send an email to [email protected] _______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected]
