Hello All, Thank you for the guidance and warnings regarding cross-flashing. Based on your recommendations, I will avoid flashing an ADL_RVP image directly onto another board and will proceed with creating a dedicated board port first.
I have another question regarding the ADL_RVP build. I am able to successfully generate a ROM image using the existing ADL_RVP configuration. However, when I try to enable and add a bootsplash image through make menuconfig, the build process stops with an error. Are there any known limitations, dependencies, or configuration requirements for bootsplash support on Alder Lake RVP platforms? I would also appreciate some guidance on GPIO configuration for a new board port. My understanding is that GPIOs must be adapted carefully before any hardware testing. Is the recommended workflow still: 1. Boot the vendor firmware. 2. Use util/inteltool to dump GPIO/pad configuration. 3. Use util/intelp2m to generate the initial GPIO definitions. 4. Create the board-specific GPIO configuration and reference it from the mainboard .cb files. Are there any examples of recent Alder Lake or Raptor Lake mainboards that demonstrate the preferred way of defining GPIO configuration in the device tree (.cb) and corresponding gpio.c/gpio.h files? Thank you again for your support and recommendations. Best Regards, Keshavamurthy K ________________________________ From: Alicja Michalska <[email protected]> Sent: Tuesday, June 16, 2026 6:30 PM To: [email protected] <[email protected]> Subject: [coreboot] Re: Request for Guidance on Coreboot Porting for Raptor Lake-S RVP + DDR5 Motherboard [You don't often get email from [email protected]. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ] Ditto, please *never* cross-flash "similar" boards. I've had people who were new to firmware development come up to me during conferences say they fried their boards by doing so (and had no idea why). On 16/06/2026 14:48, Florian Jung via coreboot wrote: > Hi Keshavamurthy, > > Am 16.06.26 um 14:12 schrieb Keshavamurthy K [Firmware-NTL] via coreboot: >> Would it be safe and appropriate to flash a Coreboot ROM generated from the >> ADL_RVP configuration directly onto the Intel ADL RVP DDR5 board for early >> testing, or would you recommend first creating a dedicated mainboard port >> and adapting the GPIO, memory, PCIe, and board-specific configuration before >> attempting any flashing? > > You absolutely need to adapt GPIO configuration. Not doing so may cause > permanent hardware damage, if GPIOs are mismatched in a way that your > firmware drives a GPIO pin while it's externally driven, too. > > There should not be any dangerous issues because of memory or PCIe-related > configuration, but you can also not expect that it'll just work. > > I'd do the porting beforehand, you'll need to do it anyway. > > Best, > Florian > > _______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected] Note : " We Never inform change of Bank details by email. If you receive any such emails from our domain/users. Please don't respond, and contact us separately "
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