Lorenzo Lutti wrote: > Question number 1: why enabling IRQ49 isn't enough? A code like this > doesn't work: > > DAVINCI_PINMUX0 &= ~(1<<26); // just in case > if( request_irq( 49,my_irq_handler, SA_INTERRUPT, "test", NULL)) > { > ... > } > set_irq_type( 49, IRQT_FALLING); > enable_irq( 49); > ... > > I've checked the registers, everything looks fine: > -EINT1 bit 17 (IRQ49 enable) is set; > -PINMUX bit 26 (CWEN) is cleared; > -DIR01 bit 1 (GPIO1 direction) is set. all good, just lose the enable_irq(), it's not necessary. > > But the ISR is never called. Why? request_irq() returns succesfully > and the kernel doesn't complain (it just output the unbalanced irq > message, which is harmless as far as I know). In 2.6.10, you need to set up the GPIO interrupt bank yourself, i.e. enabling and acknowledging the GPIO IRQ in the correct bank manually. > > > Question number 2: why in the 2.6.19 kernel the IRQ numbers for GPIOs > have been translated? For example, GPIO1 (which is IRQ49) in the new > kernel becomes the interrupt number 65. ... the GPIO interrupt banks are treated as a chained interrupt controller, hence the translation. > > Thank you! > > Cheers, Lorenzo > _______________________________________________ > Davinci-linux-open-source mailing list > Davinci-linux-open-source@linux.davincidsp.com > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
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