Hi,
I wrote and used this code on 2.6.10 with some simple porting from git
tree
(pay attention to set_rising):
int gpio_request_irq(unsigned int gpio, irqreturn_t (*handler)(int, void
*, struct pt_regs *),
unsigned long irq_flags, const char * devname, void
*dev_id)
{ FNSTART;
struct gpio_controller *__iomem g = gpio2controller(gpio);
/*
struct clk *clk;
clk = clk_get(NULL, "gpio");
if (IS_ERR(clk)) {
printk(err1, PTR_ERR(clk));
return 0;
}
clk_enable(clk);
*/
board_setup_psc(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_GPIO, 1); //
activate GPIO
//__raw_writel(0, &g->clr_rising);
//__raw_writel(0, &g->clr_falling);
__raw_writel(gpio_mask(gpio), &g->set_rising);
//__raw_writel(0, &g->set_falling);
// BINTEN -- per-bank interrupt enable.
__raw_writel(0x1f, (void *__iomem)
IO_ADDRESS(DAVINCI_GPIO_BASE + 0x08));
return request_irq(IRQ_GPIO0+gpio, handler, irq_flags, devname,
dev_id);
}
--
Constantine Shulyupin
Embedded Linux Consultant
054-4234440
http://linuxdriver.co.il/
On Fri, 2007-05-04 at 14:07 +0200, Lorenzo Lutti wrote:
> Matthias Welwarsky ha scritto:
>
> >> But the ISR is never called. Why? request_irq() returns succesfully
> >> and the kernel doesn't complain (it just output the unbalanced irq
> >> message, which is harmless as far as I know).
> > In 2.6.10, you need to set up the GPIO interrupt bank yourself, i.e.
> > enabling and acknowledging the GPIO IRQ in the correct bank manually.
>
> Do you mean that I have to use the GPIO BANK0 interrupt (which to my
> knowledge is a complete different thing) instead of the single GPIO0..7
> interrupts?
>
> Anyway I tried also with the BANK0 interrupt (interrupt number 56 and BINTEN
> bit0 set), but it doesn't work as well. The problem is that the IRQ1 register
> always has the value 0xFFFFFFFF (no interrupts received), therefore one of
> these two cases applies:
>
> 1) For some reason the interrupt never fires up and so it's never serviced;
> 2) Some other ISR handling function in the kernel services the interrupt (and
> sets IRQ1), without "forwarding" the control to my ISR.
>
> I'm going to put some printk() here and there in the kernel interrupt
> handling code to check if this last one is the case. Anyway, I'm noticing
> right now that in SPRUE14 (ARM reference guide) the last 16 bits of IRQ1 and
> EINT1 are marked as "reserved" and read-only. Apparently only the interrupts
> from 0 to 47 are officially supported. This is most probably one
> documentation error anyway; actually you can set all the 32 bits of EINT1
> without problems, and the same document states that there are 64 interrupts,
> so how would I be supposed to setup the interrupts from 48 to 64? :)
>
> Cheers, Lorenzo
>
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