On Wednesday 04 February 2009, Troy Kisky wrote:
> > + if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE)
> > + iowrite8_rep(host->base + DAVINCI_MMCDXR, p, n);
> > + else
> > + ioread8_rep(host->base + DAVINCI_MMCDXR, p, n);
> > host->buffer = p;
> > }
> >
> Are you sure this works? MMCFIFOCTL has a field "ACCWD" which
> determines the CPU/EDMA fifo access width. I would call the 32 bit rep
> routine followed by 1 more 32 bit write if a non-multiple of 4 was
> given.
As I said: "it compiles". However, if ACCWD mattered (I looked
at that a long time back), the *current* code would be incorrect
too. That field actually affects how the full/empty flags get
set, not the "access width" implied.
Can't use io{read,write}32_rep() without knowing (a) that "p"
is aligned on a 32-bit boundary, (b) that "n" is a multiple of
four bytes. In the same way, the current ASM code seems buggy
since it assumes that "p" is 16-bit aligned.
- Dave
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