Jayakrishnan, The bit field in GBLCTL register that you are trying to set is synchronized and latched by the corresponding clock(ACLKX in your case).
Since you want to use AHCLKX1 as master clk for another device I suspect the ACLKX is not already running. If you don't have ACLKX externally generated you need to select the internal clk source in ACLKXCTL (and possibly even in AHCLKXCTL - depends on the use case) before GBLCTL is programmed. Regards, Vaibhav -----Original Message----- From: Jaya krishnan [mailto:jaya.krish...@samsung.com] Sent: Monday, May 10, 2010 2:48 PM To: davinci-linux-open-source@linux.davincidsp.com; Bedia, Vaibhav Subject: DM6467 McASP : unable to set GBLCTL for port1 I want to use AHCLKX1 (from port 1) to be used as master clk for another device in the system. But I am not able to set GBLCTL. for port 1 bit= 1<<9; bit &= 0x1f00; mcasp_port[port].mcasp_vregs->gblctlx |= bit; while ((mcasp_port[port].mcasp_vregs->gblctlx & bit) != bit); It does come out from the while loop. But for port 0 no such problem. Pls help Jayakrishnan M M Research Engineer R&D Team-2 , Group-5 Security Solutions Division SAMSUNG TECHWIN CO.,LTD TEL +82-70-7147-8482 FAX +82-31-8018-3712 Mobile +82-10-6409-3619 E-mail:jaya.krish...@samsung.com _______________________________________________ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
