I had a quick look at the tools. They convert a floorplan description into a bitstream and back. However for a complete workflow the following bits are missing:
* VHDL/verilog compiler to netlist * place and route tool to turn the netlist into a floorplan Is this correct? Thanks, Peter. -- To UNSUBSCRIBE, email to [email protected] with a subject of "unsubscribe". Trouble? Contact [email protected]
